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      システム設計/検証 概要

      Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

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      デジタル設計/サインオフ 概要

      Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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      カスタムIC/アナログ/RF設計概要

      Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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      ICパッケージ設計/解析 概要

      Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

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      PCB 設計/解析概要

      Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • Spectre Accelerated Parallel Simulator

Spectre Accelerated Parallel Simulator

Delivering advanced SPICE-accurate simulation

Spectre Accelerated Parallel Simulator Datasheet

Rohde & Schwarz Case Study

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Key Benefits

  • Provides 10X-100X the single-thread performance (10X over the Spectre baseline) with out-of-box SPICE accuracy and convergence
  • Enables high-precision simulation for large, post-layout analog designs and subsystems that have a high ratio of passive to active devices—without compromising accuracy
  • Delivers scalable performance with a multi-core architecture, allowing higher levels of analog design integration and verification
  • Uses foundry-certified device models (common across all simulation engines in the Virtuoso Multi-Mode Simulation solution) to ensure silicon-accurate analog designs
  • TÜV SÜD “Fit for Purpose – TCL1” certified to meet ISO 26262 automotive functional safety requirements

Scalable performance and capacity—at full Spectre accuracy—for complex analog, RF, and mixed-signal blocks and subsystems with tens of thousands of devices.  

The Cadence® Spectre® Accelerated Parallel Simulator performs advanced SPICE-accurate simulation for faster convergence on design goals while offering scalable performance and capacity. It is tightly integrated with the Cadence Virtuoso® custom design platform, allowing engineers to capture and pass design intent in the same environment, and it provides all the transistor-level analysis capabilities of the Spectre Circuit Simulator.

The proprietary full-matrix solving technology in the Spectre Accelerated Parallel Simulator delivers unparalleled scalability and multi-threading capability using modern multi-core compute platforms. These features and more ensure precise simulation without sacrificing accuracy of results.

Automotive TCL1 Certified for ISO 26262

The industry’s first analog/mixed-signal design implementation and verification flow to achieve “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification enables you to meet stringent ISO 26262 automotive safety requirements. The analog/mixed-signal design implementation and verification flow brings transistor-level designs from creation and simulation through physical implementation and verification using the Virtuoso ADE Product Suite and the Spectre Circuit Simulation Platform. For information on the safety manuals, Tool Confidence Analysis (TCA) documents, and compliance reports from TÜV SÜD, download the Functional Safety Documentation Kits through Cadence Online Support.

  • Related Products

    • Spectre Circuit Simulator
    • Spectre eXtensive Partitioning Simulator (XPS)
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Resource Library VIEW ALL

Customers Success (2)

  • Cadence and Texas Instruments Success Story
  • Cadence and Rohde & Schwarz Success Story

Video (1)

  • Combined MathWorks and Cadence Design Flow for Analog/Mixed-Signal IC Development

Press Releases (2)

  • ケイデンス、TSMCと協業、7nm FinFET Plus設計の技術革新を加速
  • ケイデンス、業界初のメモリー設計・検証向け統合ソリューション、Legato Memory Solutionを発表

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  • Combined MathWorks and Cadence Design Flow for Analog/Mixed-Signal IC Development
News ReleasesVIEW ALL
  • ケイデンス、TSMCと協業、7nm FinFET Plus設計の技術革新を加速 09/12/2017

  • Cadence Collaborates with TSMC to Advance 7nm FinFET Plus Design Innovation 09/11/2017

  • ケイデンス、業界初のメモリー設計・検証向け統合ソリューション、Legato Memory Solutionを発表 09/07/2017

  • Cadence Announces Legato Memory Solution, Industry’s First Integrated Memory Design and Verification Solution 09/06/2017

  • Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production 03/14/2016

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