- Incisive Enterprise Simulator (50)
- System Design and Verification (41)
- Simulation and Testbench Verification (18)
- Incisive Specman Elite (11)
- SimVision (9)
- Incisive vManager Solution (9)
- Flows SDV (6)
- Palladium Z1 Series (6)
- Planning and Management (5)
- Indago Debug Platform (4)
- Incisive Functional Safety Simulator (4)
- Power-Aware Verification Methodology (4)
- Debug Analysis (4)
- Indago Debug Analyzer App (4)
- Palladium XP Series (3)
- Cadence RocketSim Parallel Simulation Engine (3)
- Xcelium Parallel Simulator (3)
- Indago Protocol Debug App (2)
- Innovus Implementation System (2)
- Indago Embedded Software Debug App (2)
- Software-driven Verification (2)
- Formal and Static Verification (2)
- Palladium Dynamic Power Analysis (2)
- Verification IP (2)
- PCB Design and Analysis (1)
- Spectre RF Simulation (1)
- Acceleration and Emulation (1)
- Spectre Accelerated Parallel Simulator (1)
- Block Implementation (1)
- Conformal Equivalence Checker (1)
- Genus Synthesis Solution (1)
- Virtuoso Analog Design Environment (1)
- Custom IC - Analog - RF Design (1)
- JaperGold Verification Platform (1)
- Protium FPGA-Based Prototyping Platform (1)
- Protium S1 FPGA-Based Prototyping Platform (1)
- Modus Test Solution (1)
- SpeedBridge Adapters (1)
- Perspec System Verifier (1)
- Virtual System Platform (1)
- Cadence VIP (1)
- System Development Suite (1)
50 Result(s) Found
Renesas used the Interconnect Workbench to accelerate performance analysis and verification of their on-chip interconnects, reducing performance analysis from 22 days to a typical 9 days.
The Interface IP are an integral part of systems-on-chips (SoC) that include mobile, automotive, or networking applications. Mixed-signal IP is primarily used for transmitting data over a physical medium b...
This white paper explores new simulator use models and methodologies that boost GLS productivity, including extraction via static timing analysis and linting. Using these approaches, designers can focus on...
This paper introduces a new way to debug that uses innovative debug concepts such as automated root-cause analysis (RCA), Big Data capture, and a unified apps-based debug analysis platform.
To examine simulation and emulation technologies for a thorough, yet faster functional verification of low-power systems on chip (SoCs), this paper first reviews the fundamental sources and reduction techn...
This application note describes new methodologies and simulator use models that increase GLS productivity, focusing on two techniques for GLS to make the verification process more effective.
A powerful, scalable, and automated verification planning and management solution supporting multi-user, multi-engine, multi-analysis, and multi-projects simultaneously
STMicroelectronics STxP70 processor technology offers a costeffective, real-time optimized, 32-bit RISC system. It can be integrated into systems on chip (SoCs) in individual or multiprocessor (MP) configu...
Cadence AVIP for PCI Express supports C++, SystemC, and UVM SystemVerilog user interfaces. Using Cadence AVIP, you can accelerate IP, subsystem, system-on-chip (SoC), and system level validation to ensure ...
Incisive verification solutions enabled RivieraWaves to easily migrate from OVM to UVM for its next-generation Bluetooth 4.1 IP designs. This enabled the company to increase automation and enable its custo...