Saving Routing Resources, Speeding Up Timing Closure at Freescale Semiconductor

How did the engineers improve these processes? Hear Nikhil Murgai, lead design engineer at Freescale Semiconductor, talk about how the team used Cadence Encounter digital implementation tools to save routing resources and speed up the timing closure process.

最終変更: February 27, 2019

期間: 4 min

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