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Silicon Signoff and Verification - 16nm FinFET Challenges and Features
Ruben Molina Product Marketing Director , Timing Signoff discusses Silicon Signoff and Verificaiton 16nm FinFE Challenges and Features. Topics include Signoff Drivers-Huge, complex mixed Signal SoC designs, Signoff inefficeiency, 16nm and FinFET
最終変更: August 22, 2015
期間: 57 min