DVCon Europe is the premier conference for functional design and verification, bringing you information from the leading edge of technology, techniques, standards, and methods. Visit Cadence in Booth 103 and we’ll introduce you to the latest tools, methodologies, and support you need for designing and verifying complex silicon, SoCs, and systems.
Join us for any of the following sessions:
- Tutorial 12: Cadence® vManager™ Platform and Virtuoso® ADE Verifier: Leading-Edge Technologies Provide the Methodology for Mixed-Signal Verification Closure
Tuesday, October 29, 14:15 - 15:45, Forum 7
- Tutorial 14: Safety- and Security-Aware Pre-Silicon Hardware/Software Co-Development
Tuesday, October 29, 16:00 - 17:30, Forum 5
- Session 3.2: The Powerful Synergy Between UVM and PSS
Wednesday, 10:45 – 12:15, Forum 6
- Session 5.2: Portable Stimuli Over UVM, Using Portable Stimuli in HW Verification Flow
Wednesday, October 30, 13:15 – 14:45, Forum 4
- Session 12.2: Processing Deliberate Verification Errors During Regression—Quis Custodiet Ipsos Custodes / Who Will Check the Checkers?
Wednesday, October 30, 15:50 – 16:45, Forum7