Length: 2 days
This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This course explores Xcelium™ integrated coverage features, with which you can measure how thoroughly your testbench exercises your design. The course addresses coverage of VHDL, Verilog and mixed-language designs. Not all coverage features are available with all languages. The course uses the Integrated Metrics Center for reporting and analysis.The course discusses the collection and analysis of the following types of coverage:
- Code (branch, expression, toggle, state, and arc) coverage
- Data-oriented functional coverage using SystemVerilog cover groups
- Control-oriented functional coverage using SystemVerilog assertions and the PSL
After completing this course, you will be able to:
- Effectively use the Xcelium integrated coverage with your VHDL, Verilog, and mixed-language designs.
Software Used in This Course
- Xcelium Single Core
- vManager Linux Client
Modules in this Course
- Introduction to Xcelium Integrated Coverage
- Identifying Coverage Types
- Identifying Code Coverage
- Defining Data Coverage with SystemVerilog Cover Groups
- Defining Control Coverage with SystemVerilog Assertions
- Defining Control Coverage with PSL Assertions
- Generating Coverage Data
- Analyzing Coverage Data Textually
- Analyzing Coverage Data Graphically
- Verification Engineers
You must have:
- Familiarity with the VHDL or Verilog languages, and with design and design verification.
- Familiarity with SystemVerilog cover groups, and SystemVerilog and PSL assertions. This course reviews them only briefly.
- VHDL Language and Application
- Verilog Language and Application
- SystemVerilog for Design and Verification
- The Xcelium Simulator