Length : 4 days
This course introduces you to using the Palladium® XP I/II verification computing platform for accelerating the verification of designs. This course is tailored based on customer requirements. Topics may include preparing a design for acceleration, improving simulation acceleration performance, creating synthesizable testbenches, an introduction to transaction-based and UVM acceleration, and design debugging using Palladium XP I/II. This course commonly uses the customer’s design as a lab platform.
After completing this course, you will be able to:
- Compile, run, and debug designs in Palladium XP I/II, in the following modes: simulation acceleration, transaction-based acceleration, UVM acceleration, and synthesizable testbench acceleration.
- Understand and improve simulation acceleration performance.
Software Used in This Course
- Unified Xcceleration Emulation (UXE)
- Incisive® Enterprise Simulator
UXE 14.1, INCISIV13.2.s2 and higher
Modules in this Course
- Palladium XP Use models, Features and Hardware
- Getting Started with Simulation Acceleration (SA)
- Improving SA Performance
- Transaction-Based Acceleration (TBA)
- Debugging a Design
- UVM Acceleration
- Verification engineers who intend to use Palladium XP I/II for acceleration
You must have experience with or knowledge of the following:
- Verilog or VHDL languages at a beginning level
- Elementary UNIX User Skills
- SystemVerilog UVM knowledge