Length : 2 days
In this course, you learn how to implement a design from RTL-to-GDSII using Cadence tools. You will start by coding a design in VHDL or Verilog. You will simulate the coded design, followed by design synthesis and optimization. You will run equivalency checks at different stages of flow. After synthesizing the design, you will floorplan, and place-and-route the synthesized netlist while meeting timing. You will run gate-level simulation throughout the flow. Finally, you will write out a GDSII file.
Note: This course is currently taught only in India region as of now
After completing this course, you will be able to:
- Code a design in Verilog to the design specification that is provided.
- Compile, elaborate and simulate your design.
- Synthesize your design.
- Design for Test.
- Run equivalency checking at different stages of the flow.
- Floorplan a design.
- Run placement, optimization, clock tree synthesis, and routing on your design.
- Run signoff checks to make sure that the design chip can be fabricated.
- Write out a GDSII.
Software Used in This Course
- INCISIVE ENTERPRISE SIMULATOR (IES)
- GENUS SYNTHESIS SOLUTION
- ENCOUNTER (R) TEST AND DIAGNOSTICS
- INCISIVE151, IC615, GENUS151, CONFRML151, ET151, INNOVUS151, QUANTUS151, SSV152
- About This Course
- Design Specification and RTL Coding Using HDL
- Functional Simulation Using the Incisive Enterprise Simulator
- Code Coverage Using Incisive Metrics Center
- Logic Synthesis Using Cadence Genus Synthesis Solution
- The Encounter Test Stage
- The Equivalency Checking Stage
- The Implementation Stage
- Gate Level Simulation
- Timing Analysis and Debug
- University students
- New hires who need to ramp up on Cadence tools
- Design engineers or verification engineers who need to learn the Cadence flow
You must have
- Knowledge of UNIX/Linux
- Basic knowledge of programming languages, for example, VHDL/Verilog/SV in order to code a simple design
- Incisive SystemC, VHDL, and Verilog Simulation
- Verilog Language and Application
- Genus Synthesis Solution
- Innovus Implementation System
- Tempus Signoff Timing Analysis and Closure
- Logic Equivalence Checking with Encounter Conformal
This classroom training is one of its kind in that it covers the complete flow from design conception to GDSII. This has been done using a very simple Verilog example keeping in mind the ease with which the students should understand the design and focus mostly on learning the flow.