Length : 2 days
The SiP RF Architect course shows you how to use a design flow between the Virtuoso® design environment and the SiP layout environment. It enables designers to create a single, system-level, circuit simulation-ready schematic for an RF/analog die, SiP substrate, and packaged and embedded discrete devices.
In this course, you learn to:
- Create and set up an RF SiP project.
- Create a symbol view and a chips view for an RF IC layout in the Virtuoso Layout Editor.
- Package a Virtuoso Schematic Editor design to generate a physical netlist for SiP layout.
- Use parameterized cells to dynamically create embedded components in your SiP layout.
- Decompose SiP layout transmission lines and backannotate them on the schematic so they can be accurately simulated.
- Generate a testbench.
- Import and assign simulation models.
- Analog IC Designers
- Package MCM Designers
- RF Designers
The labs for this course require:
- Virtuoso Schematic Editor 6.1.3
- Virtuoso Layout Editor 6.1.3
- SiP RF Architect 16.2
- SiP RF Layout 16.2
System Requirements for Online Courses
- Cadence software installed and licensed
- Make sure you install and license the Cadence® software for the system where you will run the lab exercises.
- SiP Digital Layout