Length : 3 days
There is increasing pressure on Hardware Designers to become bi-lingual. Design reuse, commercial Intellectual Property and distributed design teams are creating language neutral design methodologies, where an engineer may use VHDL for writing testbenches; Verilog and VHDL for RTL design and Verilog for gate level simulation.
Verilog for VHDL is an intensive course in Verilog for engineers who already have experience of VHDL. Based on Esperan's high-quality Verilog language and application training and delivered by trainers especially chosen for their in-depth knowledge of both languages, this course is the fastest and most effective method for VHDL engineers to understand the intricacies of Verilog and become proficient in the language.
- To provide a complete understanding of the essential concepts of Verilog and how these differ from VHDL.
- To give you practical experience of writing Verilog for synthesis and verification
- To give you the knowledge to approach your Verilog or dual language design project with confidence
This course is designed for developers who create designs for analog or digital ICs such as:
- IC Designers
- Analog/Mixed-Signal IC Designers
- Digital IC Designers
- ASIC Designers
- Design Engineers
- Chip Designers
- Layout Designers
- This course assumes prior knowledge of VHDL, for example from attendance at VHDL Language and Application
- Through real-life examples, see how to effectively deploy the models you have created in your design flow. Examples of mixed-signal models created are:
- Alarm clock,
- Verilog language introduction
- Modules; creating hierarchy; procedures; compilation; comments; identifier rules
- Data-types and Logic System
- Logic value system; data types; vectors; literals; net and register types; parameters; arrays
- Verilog Operators
- Introduction to Verilog operators.
- Procedural and Continuous Statements
- Inital and always; procedural assignment; event control; if and case(x|z); loops; continuous assignments; multiple continuous and procedural assignments
- Procedural Statements and the Simulation Cycle
- Blocking and non-blocking assignment; simulation cycle summary; event, wait and delay based timing control; timescale directive; simulation race conditions.
- Blocking and Non-Blocking Statements
- Issues and guidelines for use of blocking/non-blocking in registered and combinational logic
- Verilog Sample Design
- Creating and verifying an RTL design.
- RTL Rules and Guidelines
- Rules for describing combinational and registered logic in Verilog; Blocking assignment in clocked procedures
- Synthesis Coding Styles
- State machine description; if and case synthesis; parallel and full case; synthesis directives; initial blocks; unsupported constructs; register and latch inference issues; tri-state inference
- Tasks and Functions
- Function declaration and call; task declaration and call; task issues;
- System Control
- Compiler directives; system tasks and functions
- Using a Verilog Test Bench
- Simple stimulus; fork and join; events; vector capture and playback; clock generation
The labs have been designed to follow on from each other over the course of the training, building on code developed in each lab to create an overall design project.
The lab sessions include
- Familiarization with simulation and synthesis tools
- Describing and verifying combinatorial logic
- Creating registered logic
- Using vector arithmetic packages
- Structural design and hierarchy
- Verification using visualization of results
- State machine design
- Verification using script driven, self-checking testbenches
- Integration and verification of a third-party IP model