Length: 1 day
The methodology that accounts for the electrical parasitics earlier in the design flow is called Electrically-Aware Design (EAD). In this course, you learn about the various layout-dependent effects (LDEs) that significantly impact designs at advanced design nodes. These LDEs come into play during device placement in the layout process.
You are introduced to an incremental simulation flow that extracts and includes parasitics early in your design. You implement this design flow, in which you run parasitic extraction and resimulate using RC values that are extracted from placement proximity and electrical routing in a layout. You also create constraints and follow a constraint-aware parasitic extraction flow.
You work with a partial layout in this course because complete placement and routing are not required for this flow. You run simulations in ADE Assembler to visualize the parasitic effects and also create electrical datasets that are needed for EM analysis.
You also run electromigration (EM) analysis and check for violations using the new EAD Browser tool in the Virtuoso® Layout Suite (VLS). You then evaluate IR drop before exploring the layoutEAD view, which is used to facilitate extraction and EM analysis.
Finally, you explore Rapid Analog Prototyping (RAP), which uses the Constraint Manager and the Circuit Prospector and lets you create module generator (Modgen) constraints used in an alternate flow to estimate LDEs from the schematic.
After completing this course, you will be able to:
- Use different simulation flows to accommodate EAD and LDE effects
- Run parasitic RC extraction from electrical data using a partial layout
- Create electrical datasets that store current information needed to perform electromigration (EM) checks and IR drop analysis
- Perform electromigration checks from the layoutEAD window in Virtuoso Layout Suite
- Understand different layout-dependent effects and how they affect devices at lower nodes
- Extract LDE parasitics and use LDE parameters for resimulation
- Use parasitic information to estimate effects in an early resimulation that also uses LDE BSIM parameters
- Create and use Modgen constraints to account for LDEs in your design
- Resimulate your design in ADEAssembler using extracted parasitic information from LDE and EAD (full or partial layout data can be used for resimulations)
Software Used in This Course
- Virtuoso Advanced Node Framework
- Virtuoso Implementation-Aware Design Option
- Virtuoso Variation Analysis Option
- Virtuoso Analog Design Environment XL
- Virtuoso Layout Suite XL and EAD
- Virtuoso Spectre® Circuit Simulator
- Cadence® Physical Verification System
IC 6.1.7 ISR13, MMSIM 15.1, PVS 15.2
Modules in This Course
- Introduction to the Electrically-Aware Design Flow
- Running Parasitic Extraction
- Saving Electrical Data Using the ADE Assembler
- Performing Electromigration Checks
- Introduction to Layout-Dependent Effects
- Parasitic Resimulations Using the ADE Assemble
- Analog Design Engineers
- Mixed-Signal Design Engineers
- Custom IC Designers
- Layout Engineers
You must have experience with Linux and the ability to work with text files in the Linux environment.
Hands-on experience with the ADE Assembler and some layout experience is a plus when doing the labs. Thus, to facilitate your learning, it is recommended that you complete the following courses:
- Virtuoso Analog Simulation: T1 The Virtuoso Analog Design XL Environment
- Virtuoso Analog Simulation: T2 Creating Sweeps and Running Corner Analysis
- Virtuoso Analog Simulation: T3 Monte Carlo Simulations Using ADEXL
- Virtuoso Analog Simulation: T4 Sensitivity Analysis and Circuit Optimization Using ADE(G)XL
- Virtuoso Schematic Editor
- Virtuoso Analog Design Environment
- Virtuoso Layout Design Basics
- Virtuoso Connectivity Driven Layout Transition