The methodology that accounts for the electrical parasitics earlier in the design flow is called electrically-aware design (EAD). In addition, in this Virtuoso® Electrically-Aware Design with Layout Dependent Effects course, you learn about the different layout-dependent effects (LDEs) that significantly impact designs at advanced design nodes. These LDEs come into play during device placement in the layout process.
You are introduced to an incremental simulation flow that extracts and includes parasitics early in your design. You implement this design flow, in which you run parasitic extraction and re-simulate using RC values, which are extracted from placement proximity and electrical routing in a layout. In addition, you create constraints and follow a constraint-aware parasitic extraction flow.
You work with a partial layout in this course, because complete placement and routing is not required for this flow. You run simulations in ADE XL to visualize the parasitic effects and also create electrical datasets that are needed for EM analysis.
You run electromigration (EM) analysis and check for violations using the new EAD Browser tool in the Virtuoso Layout Suite (VLS). A layoutEAD view has been added to the VLS in IC 6.1.6 to facilitate extraction and EM analysis.
Rapid Analog Prototyping (RAP), which uses the Constraint Manager and the Circuit Prospector, lets you create module generator (modgen) constraints used in an alternate flow to estimate LDEs from the schematic.
After completing this course, you will be able to:
- Use different simulation flows to accommodate EAD and LDE effects.
- Run parasitic RC extraction from electrical data using a partial layout.
- Create electrical datasets that store current information needed to perform electromigration (EM) checks.
- Perform electromigration checks from the layoutEAD window in Virtuoso Layout Suite.
- Understand different layout-dependent effects and how they affect devices at lower nodes.
- Extract LDE parasitics and use LDE parameters for resimulation.
- Use parasitic information to estimate effects in an early resimulation that also uses LDE BSIM parameters.
- Create and use modgen constraints to account for LDEs in your design.
Software Used in This Course
- Virtuoso Advanced Node Framework
- Virtuoso Implementation-Aware Design Option
- Virtuoso Variation Analysis Option
- Virtuoso Analog Design Environment -XL
- Virtuoso Layout Suite -XL and EAD
- Virtuoso Spectre® Circuit Simulator
- Cadence® Physical Verification System
- IC 6.1.6 ISR12, MMSIM 14.1, PVS 15.1
- About This Course
- Introduction to the Electrically-Aware Design Flow
- Running Parasitic Extraction
- Saving Electrical Data Using ADE XL
- Performing Electromigration Checks
- Introduction to Layout-Dependent Effects
- Parasitic Resimulations Using ADE XL
- Analog Design Engineers, Mixed-Signal Design Engineers, Custom IC Designers, Layout Engineers
You must have experience with Linux and the ability to work with text files in the Linux environment.
Hands-on experience with ADE XL and some layout experience is a plus when doing the labs. Thus, to facilitate your learning, it is recommended that you complete the following course:
Virtuoso Analog Simulation Techniques
Virtuoso Parasitic Aware Design and Circuit Optimization
Virtuoso Simulation for Advanced Nodes