Length : 2 days
In this course, you learn the basic rules and syntax used for writing Physical Verification Language (PVL) rules. These include inputs, outputs, runset structures, and differences from Assura® rule writing, introduction to new commands, and examples of new command usage.
After completing this course, you will be able to:
- Overview of PVS Products & Setup
- Setup & Run PVS in GUI & batch mode
- Setup, Run and Debug PVS-DRC
- Setup, Run and Debug PVS-LVS
- Examine the inputs to PVS & outputs from PVS
- Check-out PVS Rule Files coded in PVL
- Analyze TCL Support in PVS
- Examine PVL data storage mechanism
- Define the Layers & Create intermediate and derived layers
- Use Boolean operators
- Select polygons and Edges based on various criteria
- Use Sizing and Layer Generation Commands
- Review ‘hierarchy manipulation’ and ‘checking Input data integrity’ in PVL
- Check out how PVS Layer Viewer works as a PVL Debugger
- Measure distance between Internal, external or Enclosure edges of polygons
- Examine Common Constraints & Arguments in PVL
- Explore Output options in PVL – in both edge and region format.
- Create sample DRC Rule Decks
- Check Antenna & Density in specific window area
- Select specific rules & Create DRC Summary File
- Check-out PVL Commands Sourced by DFM Engine
- Add, define, over-write, port and attach Texts in Layout
- Locate soft-connect & Text short violations in PVS-LVS
- Define Virtual Connect & Incremental Connectivity
- Compute properties like area, count, pereimeter etc.
- Extract properties like location, string value of a text, net ID etc.
- Extract devices like MOS, Bipolar, Resistor, Capacitor, Diode etc.
- Examine PVL commands that creates data for Parasitic Extraction.
- Perform ERC check by flagging Nets with Valid Path to other Nets or PG
- Promote User Named Devices to standard Devices
- Create LVS Report
- Explore H-Cell settings
- Check-out filtering options in LVS
- Reduce Devices by merging those connected in parallel or series
- Compare LVS parameters
- Enable Color Aware Functionality in PVS-LVS
- Explore aucdl, aulvs and Create CDL settings in PVS–LVS and compare those netlists.
- Use an existing CDL File for PVS–LVS run
- Handle X and define prefix in the source netlists.
- Modify netlisting options using .simrc file.
Software Used in This Course
- Cadence® Physical Verification System Design Rule Checker XL
- Cadence Physical Verification System Graphic LVS Debugger
- Cadence Physical Verification System Interactive Short Locator Option
- Cadence Physical Verification System Results Manager
PVS152, IC617, ASSURA41, EXT152
Modules in this Course
- Introduction to Physical Verification System (PVS)
- Layer Processing
- DRC Rules
- Layout Extraction
- ERC and LVS Rules
- Schematic Netlisting
- Preparation for PVS-QuantusFlow
- PVS Configurator
- LVS Debugging Tips
- CAD or PDK engineers who write the PVS rule decks/files
You must have:
- Familiarity with process rules and physical layout design
- To be comfortable writing commands that let you discover where design rules have been violated
- To be able to make or use a layout cell that can demonstrate the effectiveness of your coding
- Physical Verification System
- Virtuoso Layout Design Basics
- Virtuoso Schematic Editor
- Using Virtuoso Constraints Effectively
- Assura Rules Writer
- Quantus QRC Transistor-Level T1: Overview and Technology Setup