Increased demand for faster, smaller, low-power chips continues to drive geometry shrinkage as one of the ways to manage the low-power, higher performance goals in smaller form factor. 40 nm chips are state-of-the-art, 32 nm and 28 nm designs are right around the corner, and companies are already planning for 20 nm (and below) flows, methodologies, and products. While these advanced process nodes promise tremendous advantages in power, performance, and design capacity, it also raises tough design challenges. These challenges include increased timing and power variability, complex layout rules, and incredibly large designs with massive amounts of IP.
A major new challenge at 20 nm (and below) is the requirement for extra masks (double patterning) to make existing lithography work at this advanced process node. Escalating data volume and denser, more complex chips are testing the limits of traditional routing architectures. Even the slightest perturbations in the design flow can cause dramatic swings in design integrity. Design teams face a predictability crisis riddled with silicon failures, performance degradation, and prolonged design schedules. And new process and design innovations, such as high-k metal gate, SOI, and 3-D packaging, are intensifying the pressures of adoption and rapid deployment.
This course takes designers through the back-end tools required to do 20 nm and below physical design, including a review of the 20 nm process and technology requirements, Multiple Patterning (MPT), wiring setup, variations of editing path segments using Create Wire, and Create Bus, streaming in/out Precolored data, device placement constraints with respect to dummy devices, diffusion rules, Track Patterns and Constraint Overrides.
The majority of this course is captured in embedded videos (25) and reflects the lab document for students who wish to either watch the videos, and/or go through the labs to reinforce what they learned from watching the videos.
After completing this course, you will be able to:
- Understand and meet the requirements for setting up and creating physical designs using Virtuoso 12.2 software at 20 nm and below.
Software Used in This Course
- ICADV 12.2
- ICADV12.2 ISR2 and above
Modules in this Course
- Advanced Node Technology Overview
- FinFET Grids, Snap Patterns, Placement, and Abutment
- VXL Layout Generation
- MPT Introduction
- Color Verification
- Advanced Node Constraints
- Width Space Patterns (WSP)
- Physical Designers, Layout Engineers
You must have experience with or knowledge of the following:
- Virtuoso Layout Suites XL and GXL
Or you must have completed the following courses:
System Requirements for Online Courses
- For system requirements click here
- Cadence software as listed above installed and licensed
- Virtuoso Platform Update Training: Physical Design
- Virtuoso Layout Suites Update Training
Before taking this course, it would be beneficial to review the ICADV 12.1 course first as there are basic concepts which will be helpful in understanding the ICADV 12.2 course.