Real Modeling with SystemVerilog

Online Courses

Instructor-Led Schedule

Date	Version	Country	Location
14 - 16 Oct 2019	18.09	Germany	Feldkirchen-Munich Germany	ENROLL
Scheduled upon demandOn demand				EXPRESS INTERESTINQUIRE

Version	Region
14.2	North America	ENROLL
	Other Regions	EXPRESS INTERESTINQUIRE

Length : 3 days

Course Description

In this advanced Engineer Explorer course, you focus on Real-Number Modeling (RNM) using the SystemVerilog language, in a mixed approach borrowing concepts from the digital and analog domains to enable high-performance digital-centric, mixed-signal verification. You must have a working knowledge of Verilog and SystemVerilog languages and experience working with the AMS Designer simulator.

In this course, you learn how to model analog block operation as discrete real data to dramatically improve top-level verification performance using SV real data type and nettypes. It stresses on SystemVerilog 2012 Extended Nettype Capabilities (built-in, UDT/UDR) and Interconnects. You learn how to use the Cadence^® package "EE_pkg" that defines nettype "EEnet" to describe analog impedance-based interactions between blocks in a SystemVerilog DMS environment. You then examine advanced RNM features, SV port connections and Connect Modules (CM) for AMS interactions. The nettype debug and performance improvement are discussed. Most of the labs in this course are in command-line mode using the Xcelium™ simulator with the mixed-signal option.

The course also covers an optional module on working with SystemVerilog text models and packages using AMS-UNL in the Virtuoso^® environment.

Learning Objectives

After completing this course, you will be able to

Identify how Real-Number Modeling (RNM) using SystemVerilog enables high-performance digital-centric, mixed-signal SoC verification
Create real-number models with SystemVerilog real variables and nettypes
Apply the real modeling techniques for creating analog operations and functions
Identify SystemVerilog 2012 Extended Nettype Capabilities (built-in, UDT/UDR) and Interconnects
Examine the Cadence package “EE_pkg” that defines nettype “EEnet" for electrical pin modeling
Explore advanced SV-RNM features and Connect Modules (CM) for AMS interactions
Identify how SV port connections are resolved in mixed designs using wildcard (.*) notation
Debug the Nettype (UDT/UDR) struct values using Tcl commands and system functions
Improve performance with incremental elaboration at SV-RNM partition boundary
Work with SystemVerilog Models and Packages in the Virtuoso environment

Software Used in This Course

Xcelium Digital Mixed-Signal Option
Xcelium AMS Option
Xcelium Single Core
Xcelium Limited Single Core
SimVision™ Waveform Display
Spectre^® AMS Designer
Spectre AMS Connector
Spectre Multi Mode Simulation with AMS
Virtuoso Schematic Editor
Virtuoso Simulation Environment
Virtuoso ADE Explorer and Assembler
Virtuoso Visualization & Analysis XL

Software Release(s)

XCELIUM 18.09 (18.09-s009), SPECTRE 17.1(ISR12), IC 6.1.8 (Base)

Modules in this Course

Introduction to Real Modeling
SV-RNM Basics
SV Real Modeling Techniques
Advanced SV-RNM Modeling Techniques
Modeling Electrical Circuits Using Cadence "EE_pkg"
SV-RNM Capabilities and Interactions
SV-RNM Debug and Performance Improvement
SV-RNM in the Virtuoso Environment (Optional)
Optional Appendixes
- SystemVerilog Basics
- SV Real Modeling Examples
- Connection of SystemVerilog (.*) Ports to AMS
- Helpful xrun Options
- Waveform Viewers

Audience

Verification engineers, verification leads, designers, and managers interested in improving the predictability, productivity, and quality of mixed-signal SoC verification runs
Analog and mixed-signal SoC verification engineers looking to learn about event-based behavioral modeling techniques
Digital and SoC verification engineers looking to achieve >100X to 500X performance improvements in their nightly regression runs

Prerequisites

You must have completed the following courses:

Related Courses

Real Modeling with Verilog-AMS

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Course ID: 85058

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Real Modeling with SystemVerilog

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