Real Modeling with SystemVerilog

This course focuses on Real-Number Modeling (RNM) using the SystemVerilog language, a mixed approach borrowing concepts from the digital and analog domains to enable high-performance digital-centric, mixed-signal verification. You must have a working knowledge of Verilog and SystemVerilog languages and experience working with the AMS Designer simulator.

In this course, you learn how to model analog block operation as discrete real data to dramatically improve top-level verification performance using SV real data type and nettypes. It stresses on SystemVerilog 2012 Extended Nettype Capabilities (built-in, UDT/UDR) and Interconnects. You learn how to use the Cadence^® package "EE_pkg" that defines nettype "EEnet" to describe analog impedance-based interactions between blocks in a SystemVerilog DMS environment. You then examine advanced RNM features, SV port connections and Connect Modules (CM) for AMS interactions. The nettype debug and performance improvement are discussed. Most of the labs in this course are in command-line mode using the Xcelium™ simulator with the mixed-signal option.

The course also covers an optional module on working with SystemVerilog text models and packages using AMS-UNL in the Virtuoso^® environment.