Real Modeling with SystemVerilog

Learning Objectives

After completing this course, you will be able to

• Identify how Real-Number Modeling (RNM) using SystemVerilog enables high-performance digital-centric, mixed-signal SoC verification
• Create real-number models with SystemVerilog real variables and nettypes
• Apply the real modeling techniques for creating analog operations and functions
• Identify SystemVerilog 2012 Extended Nettype Capabilities (built-in, UDT/UDR) and Interconnects
• Examine the Cadence package “EE_pkg” that defines nettype “EEnet" for electrical pin modeling
• Explore advanced SV-RNM features and Connect Modules (CM) for AMS interactions
• Identify how SV port connections are resolved in mixed designs using wildcard (.*) notation
• Debug the Nettype (UDT/UDR) struct values using Tcl commands and system functions
• Improve performance with incremental elaboration at SV-RNM partition boundary
• Work with SystemVerilog Models and Packages in the Virtuoso environment

• Xcelium Digital Mixed-Signal Option
• Xcelium AMS Option
• Xcelium Single Core
• Xcelium Limited Single Core
• SimVision™ Waveform Display
• Spectre^® AMS Designer
• Spectre AMS Connector
• Spectre Multi Mode Simulation with AMS
• Virtuoso Schematic Editor
• Virtuoso Simulation Environment
• Virtuoso ADE Explorer and Assembler
• Virtuoso Visualization & Analysis

Software Release(s)

XCELIUM 19.09 (19.09-s002), SPECTRE 18.1(ISR8), IC 6.1.8 (ISR6)

Modules in this Course

• Introduction to Real Modeling
• SV-RNM Basics
• SV Real Modeling Techniques
• Advanced SV-RNM Modeling Techniques
• Modeling Electrical Circuits Using Cadence "EE_pkg"
• SV-RNM Capabilities and Interactions
• SV-RNM Debug and Performance Improvement
• SV-RNM in the Virtuoso Environment (Optional)
• Optional Appendixes
  • SystemVerilog Basics
  • SV Real Modeling Examples
  • Connection of SystemVerilog (.*) Ports to AMS
  • Helpful xrun Options
  • Waveform Viewers

Audience

• Verification engineers, verification leads, designers, and managers interested in improving the predictability, productivity, and quality of mixed-signal SoC verification runs
• Analog and mixed-signal SoC verification engineers looking to learn about event-based behavioral modeling techniques
• Digital and SoC verification engineers looking to achieve >100X to 500X performance improvements in their nightly regression runs

Prerequisites

You must have a working knowledge of Verilog and SystemVerilog languages and experience working with the AMS Designer simulator and have completed the following courses:

• SystemVerilog for Design and Verification
• Mixed-Signal Simulations Using Spectre AMS Designer
• Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
  

Related Courses

• SystemVerilog for Design and Verification
• Mixed-Signal Simulations Using Spectre AMS Designer
• Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
• Real Modeling with Verilog-AMS
• Mixed Signal IP and Testbench Reuse
  

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