Length : 2 days
During this course, the student will learn the basic skills necessary to characterize and validate standard cell libraries using both Cadence Library Creation and Cadence Library Validation software tools. The course consists of both lecture and labs.
After completing this course, you will be able to:
- Create Liberty, Verilog, Vital and datasheet library views.
- Characterize Standard Cells for timing, power and noise.
- Use different algorithms for characterizing timing, power and noise.
- Validate Liberty libraries for correctness, consistency and accuracy.
- Explore differences between library data.
- Identify and Debug failed characterization data.
Software Used in This Course
- About this Course
- Introduction to CLC
- Building a Library from Scratch
- Library Re-characterization
- Characterization Methods for Timing, Power and Noise
- Creating Current Source Mode
- Validating Libraries with CLV
- Debugging Characterization Issues
- Design engineers or CAD engineers who are responsible for creating libraries to use in front-end design flows.
You must have:
- A working knowledge of Liberty Syntax.
- An understanding of transistor level simulation and syntax.
- A basic knowledge of TCL programming.
Virtuoso Analog Simulation Techniques