Length : 2 days
Course Description
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In this course, which has been designed for user-level physical design verification, you run DRC, ERC, PERC, FastXOR and LVS checks to find and debug errors that are located during the checks. You set up options, run DRC, and use the debugger to locate and fix design rule violations. You set up and run ERC, use the debugger, and run the interactive short locator to find and fix errors. You set up options, run LVS, and use the LVS debug environment to locate and repair errors. You also explore the documentation system and Cadence® online support.
In this course, the Virtuoso® Layout Suite is used. The Physical Verification System (PVS) is integrated into the Virtuoso menus for easy access. You set up and run IPVS for post-edit DRC checking, and use FastXOR to compare a stream file with an existing OpenAccess cellview.
The final module of the course has a free-form lab exercise, which is to be done using the skills that you learned in the previous modules. You have a physical layout with multiple errors and you have minimal instructions. You find and fix the errors, so you have clean DRC, ERC, and LVS runs.
Learning Objectives
After completing this course, you will be able to:
- Check out where PVS fits in the Cadence SSV Solution
- Overview the features and capabilities in PVS
- Explore the Advanced Debug solutions in PVS
- Setup and Run PVS DRC in GUI and batch modes
- Explore the PVS Configurator feature
- Examine the PVS DRC Waivers flow
- Explore the PVS QuickView platform
- Set up and run PVS ERC in GUI and batch modes
- Define and debug Stamping Conflicts
- Set up and run PVS PERC in GUI and batch modes
- Explore topology checks from PVS PERC
- Set up and run PVS LVS in GUI and batch modes
- Clean Shorts with Interactive Shorts Locator
- Troubleshoot LVS violations with Graphical LVS Debugger
- Set up and run VIPVS in Post-Edit and Verify-Design modes
- Create and manage snapshots for VIPVS
- Run VIPVS in Dynamic Rules Filtering mode
- Understand the concept of Constraint Validation in PVS
- Invoke, set up and run PVS CV in Virtuoso platform
- Debug Constraint Violations with DRCDE and Annotation Browser
- Explore various type of constraints supported by PVS CV
- Set up and run PVS FastXOR in GUI and batch modes
- Debug Design violations with PVS Debug environment
- Review PVS Tips and reference info on Cadence Online Support
Software Used in This Course
- Virtuoso Layout Suite
- Physical Verification System
Software Release(s)
PVS152, IC617, ICADV122, ASSURA41
Modules in this Course
PVS IntroductionDesign Rule CheckingElectrical Rules CheckingProgrammable ERCLayout Versus SchematicVirtuoso Interactive PVSConstraint Validation in PVSRunning FastXORExtended Practice for DRC, ERC and LVS
Audience
- Physical layout designers who need to verify layout designs
Prerequisites
You must have:
- Knowledge and experience with physical design and verification
- Familiarity with the Virtuoso Layout Suite
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
Course ID: 84509
