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Physical Verification System
Date | Version | Country | Location | |
---|---|---|---|---|
06 - 07 Mar 2019 | 16.1 | Israel | Petah-Tikva-Tel Aviv Israel |
ENROLL |
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
---|---|---|
16.1 | North America | ENROLL |
14.1 | North America | ENROLL |
Other Regions | EXPRESS INTERESTINQUIRE |
Length : 2 days
Course Description
Click here for Course Preview.
In this course, which has been designed for user-level physical design verification, you run DRC, LVS,ERC, PERC, FastXOR and Constraint Validation checks to find and debug errors that are located in your design. You set up options, run DRC, and use PVS DRC Results Viewer or DRC DE to locate and fix design rule violations. You set up, run and debug ERC violations including stamping conflicts.You set up options, run LVS, and use the LVS debug environment to locate and repair errors like shorts and opens. You also run the Interactive Shorts Locator (ISL) to spot shorting locations. You will set up constraints using the Virtuoso® Constraint Manager and validate them with the PVS Constraint Validator. You then set up and run VIPVS (Virtuoso Integrated PVS) in Post-Edit and Verify-Design modes for in-design instant DRC checking, and use FastXOR to compare a stream file with an existing OpenAccess cellview.
In this course, the Virtuoso Layout Suite is used. The Physical Verification System (PVS) is integrated into the Virtuoso menus for easy access. The "Extended Practice" module of this course has a free-form lab exercise, which is to be done using the skills that you learned in the previous modules. You have a physical layout with multiple errors and you have minimal instructions. You find and fix the errors, so that you have clean DRC, ERC, and LVS runs.
Learning Objectives
After completing this course, you will be able to:
Software Used in This Course
- Virtuoso Layout Suite
- Physical Verification System
Software Release(s)
PVS161, IC617, ICADV123
Modules in this Course
- PVS Introduction
- Design Rule Checking
- Electrical Rules Checking
- Programmable ERC
- Layout Versus Schematic
- Virtuoso Interactive PVS
- Constraint Validation in PVS
- Running FastXOR
- Extended Practice for DRC, ERC and LVS
Audience
- Physical layout designers who need to verify layout designs
Prerequisites
You must have:
- Knowledge and experience with physical design and verification
- Familiarity with the Virtuoso Layout Suite
Related Courses
- Virtuoso Schematic Editor
- Virtuoso Layout Design Basics
- Virtuoso Connectivity-Driven Layout Transition
- Using Virtuoso Constraints Effectively
- Physical Verification Language Rules Writer
- Assura® Verification
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
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“A well structured course with very patient instructor. Indeed will be taking home a lot of inputs from this 2 day course to help me and my colleague's future work at our organization. Looking at my fellow participants at the course, it feels like 'Yes we are in the game'..”
Thanuchith Vakkaliga-Raju, IMMS

“The course was efficient and very helpful for our Designers. For sure it will contribute to our productivity improvement.”
Mounir Jouini, EMMicroelectronic