Course Description
In this course, you run DRC, LVS, ERC, PERC, FastXOR and Constraint Validation checks to find and debug errors. You set up options, run DRC, and use PVS DRC Results Viewer or DRC DE to locate and fix design rule violations. You set up, run and debug ERC violations including stamping conflicts. You set up options, run LVS, and use the LVS debug environment to locate and repair errors like shorts and opens. You also run the Interactive Shorts Locator (ISL) to spot shorting locations. You set up constraints using the Virtuoso® Constraint Manager and validate them with PVS Constraint Validator. You then set up and run VIPVS (Virtuoso Integrated PVS) in Post-Edit and Verify-Design modes for in-design instant DRC checking, and use FastXOR to compare stream file with existing OpenAccess cellview.
In this course, the Virtuoso Layout Suite is used. The Physical Verification System (PVS) is integrated into Virtuoso menus.
The "Extended Practice" module has free-form lab exercise. You have a physical layout with multiple errors and you have minimal instructions. You find and fix the errors, so that you have clean DRC, ERC, and LVS runs.
Learning Objectives
After completing this course, you will be able to:
- Check where PVS fits in the Cadence SSV Solution
- Overview the features and capabilities in PVS
- Explore the Advanced Debug solutions in PVS
- Set up and run PVS DRC in GUI and batch modes
- Explore the PVS Configurator feature
- Examine the PVS DRC Waivers flow
- Explore the PVS QuickView platform
- Set up and run PVS ERC in GUI and batch modes
- Define and debug Stamping Conflicts
- Set up and run PVS PERC in GUI and batch modes
- Explore topology checks from PVS PERC
- Set up and run PVS LVS in GUI and batch modes
- Clean shorts with the Interactive Shorts Locator
- Troubleshoot LVS violations with the Graphical LVS Debugger
- Set up and run VIPVS in Post-Edit and Verify-Design modes
- Create and manage snapshots for VIPVS
- Run VIPVS in Dynamic Rules Filtering mode
- Understand the concept of Constraint Validation in PVS
- Invoke, set up and run PVS CV in the Virtuoso platform
- Debug Constraint Violations with DRCDE and Annotation Browser
- Run PVS CV and debug violations in the Virtuoso Constraint Manager
- Explore various type of constraints supported by PVS CV
- Set up and run PVS FastXOR in GUI and batch modes
- Debug design violations with the PVS debug environment
- Review PVS tips
Software Used in This Course
Virtuoso Layout Suite IC617, Physical Verification System PVS161, ICADV123
Modules in this Course
PVS Introduction, Design Rule Checking, Electrical Rules Checking, Programmable ERC, Layout Versus Schematic, Virtuoso Interactive PVS, Constraint Validation in PVS, Running FastXOR, Extended Practice for DRC, ERC and LVS
Audience
Physical layout designers who need to verify layout designs
Prerequisites
You must have:
Knowledge and experience with physical design and verification, Familiarity with Virtuoso Layout Suite
