Length : 2 days
This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This training provides an introduction to the concepts, challenges, and techniques for simulating and verifying low-power designs. It instructs how to communicate your design's low-power features to the simulator and downstream tools with the Common Power Format (CPF). It highlights the power-aware features of the Incisive® Enterprise family simulation and verification management tools.
After completing this course, you will be able to:
- Use digital simulation to verify power control design elements
Software Used in This Course
- EMG100 Incisive Enterprise Manager
- 29651 Incisive Enterprise Simulator - XL
- Incisive 13.1
Note that this course can be tailored to better meet your needs – contact the Cadence training staff for specifics.
- Course Introduction
- Introduction to Power-Aware Simulation
- Introduction to the Common Power Format
- Simulating a CPF-Based Power-Aware RTL Design
- Adding Power Modes to Your CPF-Based Power Simulation
- Instantiating Power-Aware Design IP
- Examining Power-Related Simulation Behavior
- Adding Power to Your Verification Plan
- Simulating a CPF-Based Power-Aware Gate-Level Design
- Conclusions and Next Steps
- Verification personnel using digital simulation to verify power-aware designs
You must have experience with or knowledge of the following:
- Using the Incisive Enterprise Simulator to simulate and debug digital designs
- (Optional) Basics of low-power CMOS design