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Conformal Constraint Designer

Conformal Constraint Designer

Instructor-Led Schedule

Date	Version	Country	Location
Scheduled upon demandOn demand				EXPRESS INTERESTINQUIRE

Length : 1 day

Course Description

In this course, you use Encounter® Conformal® Constraint Designer to manage constraints for complex system-on-a-chip designs from RTL through layout. To avoid poorly written or mismatched constraints that result in bad silicon, you validate the constraints by checking the structure, syntax, and implementation.

During chip integration, constraints might conflict in terms of clock definition, input and output delay settings, and exceptions. You learn to detect these errors earlier in the design cycle by using hierarchical constraint checks. You also automatically generate and validate false path exceptions from critical paths by applying functional validation.

Learning Objectives

After completing this course, you will be able to:

Identify the flow of the constraint design and verification
Create SDCs using template generation and using SDC Advisor
Debug SDC lint
Debug structural and other SDC violations using the Helix Rule Manager
Analyze clock domain crossing issues

Software Used in This Course

Conformal Constraint Designer

Software Release(s)

CONFRML162

Modules in this Course

Introduction to the Constraint Designer Software
SDC Generation
SDC Lint Checks
SDC Policy Checks
Clock Domain Crossing

Audience

Design Engineers
Logic Designers

Prerequisites

You must have experience with or knowledge of the following:

Static Timing Analysis
Standard Design Constraints (SDC)

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Click here to view course learning maps, and here for complete course catalogs.

Course ID: 82142

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