This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This course explores Incisive® comprehensive coverage features, with which you can measure how thoroughly your testbench exercises your design. The course addresses coverage of VHDL, Verilog, and mixed-language designs. Not all coverage features are available with all languages. The course uses the Incisive Metrics Center for reporting and analysis.
The course discusses the collection and analysis of the following types of coverage:
- Code (block, expression, toggle, state, and arc) coverage
- Data-oriented functional coverage using SystemVerilog cover groups
- Control-oriented functional coverage using SystemVerilog assertions and the PSL
After completing this course you will be able to:
- Effectively use the Incisive comprehensive coverage with your VHDL, Verilog, and mixed-language designs
Software Used in This Course
- Incisive Enterprise Simulator - XL
Modules in this Online Course
This training consists of ten modules:
- Introduction to Incisive Comprehensive Coverage
- Identifying Coverage Types
- Identifying Code Coverage
- Defining Data Coverage with SystemVerilog Cover Groups
- Defining Control Coverage with SystemVerilog Assertions
- Defining Control Coverage with PSL Assertions
- Generating Coverage Data
- Textually Analyzing Coverage Data
- Graphically Analyzing Coverage Data
- Conclusions and Next Steps
- Verification Engineers
You must have:
- Familiarity with the VHDL or Verilog languages, and with design and design verification.
- Familiarity with SystemVerilog cover groups, and SystemVerilog and PSL assertions. This course reviews them only briefly.
System Requirements for Online Courses
- Cadence software as listed above installed and licensed