This is a half-day introduction to the concepts and terminology of Automatic Test Pattern Generation (ATPG) and Digital IC Test.
After completing this course, you will be able to:
- Understand and be able to discuss why we test, what we test, and how we test, including:
- The difference between defects and faults
- The fault models commonly used
- How patterns are generated for combinational, sequential, and scanned circuits
- Basic DFT design rules
- Special tests such as for memory, cores, self-test, compression, I/Os, etc.
- Test escapes and their effect on test volume and product quality
- Basic diagnostics capabilities
Software Used in This Course
Modules in this Course
- The Basics:
- The Purpose of Test
- The Target of Test
- The Basics of Test
- VHDL Designers
- Logic Designers
- Library Developers
- IC Designers
- Hardware Engineers
- Engineering Managers
- Electrical Engineers
- Digital IC Designers
- Design for Testability Engineers
- Design Engineers
- Custom Circuit Designers
- Chip Designers
- Cadence Application Engineers
- ASIC Designers
- CAD System Administrators
- CAD Engineers
This class is open to anyone with a curiosity about the basics of testing digital ICs. Anyone involved in digital IC design or support can benefit from it.
There are no prerequisites for taking this class.
System Requirements for Online Courses
- Cadence software installed and licensed
This course contains no audio.
This class or equivalent practical experience is a prerequisite for all Encounter Test classes.