Length : 3.5 days
The DARPA Circuit Realization at Faster Timescales (CRAFT) program seeks to dramatically shorten the design and verification cycle for custom integrated circuits. This course will cover the techniques and tools being developed for the CRAFT program by UC Berkeley and Cadence Design Systems. The crux of the approach is to capture design and verification engineers' methodologies and knowledge in the form of executable generators, thus enabling rapid iteration, parameter changes, and incremental extension. In this course, students will learn the basics of the CRAFT flow: CHISEL - an open-source hardware construction language, BAG – the Berkeley Analog Generator, and Verification Work Bench – the Cadence tool for automating the verification flow with input from CHISEL (IPXact), and the integrated Cadence implementation flow.