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- Improved verification planning results in higher quality
- Metrics analysis and reporting increase schedule predictability
- Failure/metrics analysis and job automation boost overall team productivity
Functional verification entails changing the state of a logic design and measuring that the response generated by the design is correct. Verification environments change the state of designs by driving stimulus in the form of directed or constrained random inputs.
Regardless of stimulus type, metric-driven verification (MDV) is about data-driven decision-making, providing clear metrics that are easily understood, to improve verification predictability, productivity, and quality. MDV is a closed-loop process, from executable verification plans (vPlan) to testbench creation, execution, and finishing with measurements and analysis to see what remains to be done (Figure 1).
Multi-engine MDV for SoC developers transparently connects metrics from all of the Cadence® verification engines, ensuring all aspects of the SoC are executed and measured. From IP to interconnects and subsystems, to software-driven testing, acceleration, emulation and FPGA prototyping, multi-engine MDV is integrated and comprehensive. Our Incisive® simulation environment provides verification depth, JasperGold® formal technologies provide verification automation, and the Palladium® platform provides verification acceleration to full-chip emulation.
Plan: The MDV solution utilizes the most powerful specific-purpose verification plan authoring software, completely integrated into the Cadence® vManager™ platform. The MDV flow starts with automated planning, either annotating existing specifications with verification intent or creating an executable verification plans using team member inputs captured in a spreadsheet. The plan specifies the verification environment requirements to be implemented in the testbench to ensure design intent can be delivered. Verification IP (VIP) provides immediate access to the plan-based MDV methodology by delivering protocol-specific verification plans and a test suite. Verification plans, or vPlans, become executable once embedded within the vManager environment. Plans can be embedded within plans, and can be parameterized for plan re-use, which improves verification productivity.
Construct: MDV spans from simple directed test methodologies, through to register-transfer level (RTL)-based coverage-driven and software-driven approaches. For RTL verification, the Universal Verification Methodology (UVM) standard has been specifically designed to provide powerful constrained random testing. For the SoC environment, the Perspec™ System Verifier provides a similar capability for software-driven test scenarios. With constrained random stimulus, vectors are automatically generated without a need to spell out each set of input vectors manually.
Constrained random stimulus brings constrained random changes in state. In this environment, it’s imperative that the verification team can specify which states have been explored, and that for those explored states, the correct response to stimulus vectors is observed. That’s why functional coverage is utilized. Functional coverage is defined for and captures scenarios that are important for the verification environment to observe and capture. As such, functional coverage serves as a guide in the process of determining the state of the verification effort and when that effort has been completed to satisfaction of the relevant stakeholders. Functional coverage is the tangible measurement of all of the features and functions you are trying to verify, and is used at IP, interconnect, subsystem, and SoC levels. As a forward-looking predictive metric of both bugs and completion rates, functional coverage is imperative to all verification teams.
Execution: Verification simulation, formal analysis, analog mixed-signal, acceleration, and emulation execution engines are dispatched, and the Cadence vManager environment manages the convergence of results from multiple verification engines. The environment:
- Analyzes and prioritizes failures
- Analyzes regressions and coverage
- Develops changes to the testbench to reach closure
Measurement/Analysis: MDV is used to measure real-time progress with on-demand information, as well as to determine when high-quality verification closure is achieved. Tests, coverage, checks, assertions, and user-defined attributes are the generic metric types used from IP to SoC, and provide the verification-specific metrics used to determine closure. Verification job failures, bugs, and design revisions all provide insight into the actual status of a project. The Cadence vManager Metric-Driven Signoff Platform is open to enterprise integration with a powerful API to connect tools, people, and processes typical in most verification environments. Progress tracking, vPlan results, web-based dashboards, and HTML reports help the verification team and managers make adjustments to their resource allocation (people and tools) to reach signoff more efficiently and measure closure more accurately.
MDV allows you to capture all of the key metrics in the verification process, from the coverage notions described previously for the device under test (DUT metrics), to the project metrics necessary to be visible and managed (Figure 2). The list of metrics available is endless, yet the MDV flow provides an executable verification plan to organize, manage, and view this overwhelming amount of metrics in a form that you can read and easily understand.
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