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- Automation, which reduces manual effort and also provides complex tests that wouldn’t be written manually
- Abstraction and ease of use, specifying system-level scenarios in an intuitive, flexible GUI that doesn’t require you to be an expert on the details of the system
- Platform support, with a reuse model and tests that work across pre-silicon and post-silicon platforms
Frustrated by all of the manual effort and time you’re spending developing complex system-level coverage-driven tests to verify your system on a chip (SoC)? Cadence® Perspec™ System Verifier automates this entire process, reducing complex use-case scenario development from weeks to just days. Compared to manual test development, you’ll be able to generate 10X more tests using this platform. In addition, with its integrated debugging capability, you’ll be equipped to reproduce, find, and fix complex SoC-level bugs in order to improve the overall quality of your SoC.
Because it applies an appropriate level of abstraction, Perspec System Verifier can meet the growing challenges of validating SoC performance, function, and power, especially at advanced nodes. The platform is portable, supporting reuse across
Using Perspec System Verifier, you'll benefit from completeness of measurement, with coverage of functionality, flows, and dependencies. You'll also gain knowledge transfer advantages, since the formal, model-based system description supports knowledge sharing between different groups, particularly hardware and software engineers.
See What Customers Have to Say About the Perspec System Verifier
- Automated Test Generation to Verify CPU Subsystem for System Level Low Power Management by Perspec by MediaTek, 2016
- Make Stimuli Portable by Using Perspec System Verifier by Texas Instruments, 2016
- Cadence Perspec System Verifier Usage at Sub-System/SoC/Silicon Level for Infineon Aurix Microcontrollers by Infineon, 2016
- SoC Verification Using Perspec SystemVerifier by Microsemi, 2016
- Enabling Verification of Complex System Scenarios Using Perspec System Verifier by STMicroelectronics, 2015
- Cadence Perspec System Verifier on a Real SoC Verification of a MSP430 Mixed-Signal-Microcontroller by Texas Instruments, 2015
- Automated Test Generation to Verify IP Modified for System-Level Power Management by STMicroelectronics, 2015
- Incremental and Configurable Verification Strategies for Modern SoCs by Samsung and Cadence, 2015
We found that the Perspec technology easily detected issues caused by complex combinations of power mode settings and transitions. The technology can help us dramatically improve productivity and deliver our designs to IoT application developers much faster.
Toshinori Inoshita, Renesas
With the Perspec approach we get a lot of interesting scenarios “for free” which are difficult to achieve in a directed test. … In case of failures, the scenario viewer helps to understand the intended execution flow.
Thorsten Klose, Infineon
[It was] easy to generate complex scenarios using [Perspec] Composer drag and drop composition and scenario completion. [The] graphical scenario representation enables collaboration.
Smitha Kaginele and Murthy Hari, Microsemi
This [Perspec] flow facilitates [absorption of] late design changes rapidly due to automation in the testbench and test case generation.
Vivek Goyal and Vijay Rajan Machingauth, Samsung
[Perspec] Verification Engineer increased confidence in power sequence support. [This] methodology could be applied to any low-power (LP) verification.
Christophe Lamard, STMicroelectronics
[Perspec] system model changes can easily regenerate all test cases. Generated stimulus code is very well readable based on templates with the same look and feel as traditional stimuli.
Frank Donner, Texas Instruments
Perspec improves RTL regression efficiency and quality, ...[and] enables software/hardware co-verification.
Hsuan-Ming Chou, Osmond Yao, and Dennis Hsu, MediaTek
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