A top-down software-driven verification approach addresses SoC-level verification requirements like vertical reuse (portable from IP to SoC levels), horizontal reuse (cross platform: portable from simulation to post-silicon), and also use-case reuse leveraging use cases from IP and subsystem experts to others tasked with verifying the full SoC. Cadence has automated test development to bring greater efficiency to software-driven verification.
What’s more, when you tap into the integrated tool suite, you’ll be able to achieve much more powerful results:
- Compiles databases for different workloads, with up to 140MG per hour compile times on a single workstation
- Allocates as many workloads as possible
- Runs workloads based on priorities
- Debugs for both pre- and post-silicon bugs