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- Provides an average 2X improved single-core performance
- Offers an average multi-core performance speed-up of 3X for RTL design simulation, 5X for GLS, and 10X for DFT simulations running on today’s servers
- Provides parallelism with multi-core speed-up, benefiting event-dense simulation runs of all types
- Further extends innovation within the Cadence Verification Suite
- Support expands from x86 CPUs to include Arm-based servers
Cadence® Xcelium™ Parallel Logic Simulation is the EDA industry’s first production-ready third-generation simulator. It is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster than current solutions. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation simulators. The Xcelium simulator is production proven, having been deployed to early adopters across mobile, graphics, server, consumer, IoT, and automotive projects.
The Xcelium simulator offers the following benefits aimed at accelerating system development:
Multi-core engine architected for fast SoC simulation
- Patented solution automatically analyzes design and selects optimal configuration for speed
- Provides an average speed-up of 3X for register-transfer level (RTL), 5X for gate-level simulation (GLS), and 10X for design for test (DFT)
Single-core engine refactored for fast IP simulation
- Proven engine runs comprehensive set of simulation use cases
- Provides an average of 2X speed-up over the Cadence Incisive® Enterprise Simulator
Productivity features enable efficient verification
- Innovative solutions on top of fast engines reduce overall project time
- Provides enhanced smart exclusion flow and parallel multi-core
The multi-core engine in the Xcelium simulator provides fine-grained design parallelism to speed-up SoC simulations that run for days or weeks in second-generation simulators.
Its unique compile/elaboration process analyzes each design’s dependency graph and automatically maps it to the optimal number of cores to maximize its speed. Users can set the number of cores on the command line without recompile. The Xcelium simulator further extends innovation within the Cadence Verification Suite, which is comprised of best-in-class core engines, verification fabric technologies, and solutions that increase design quality and throughput, thus fulfilling verification requirements for a wide variety of use cases and vertical segments.
Press Releases (5)
- Cadence and Arm Deliver First SoC Verification Solution for Low-Power, High-Performance Arm-Based Servers
- Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
- Teradyne Standardizes on Cadence Xcelium Parallel Logic Simulator
- Cadence Launches Protium S1 FPGA-Based Prototyping Platform for Early Software Development
- Cadence Launches Xcelium Parallel Simulator, the Industry’s First Production-Proven Parallel Simulator
The Xcelium Parallel Simulator has demonstrated a 4X speed-up for gate-level simulation and 5X for RTL simulation on ARM®-based SoC designs. Based on these results, we expect Xcelium can enhance our ability to deliver the most complex SoCs in a fast and highly reliable way.
Hobson Bullman, general manager, Technology Services Group, ARM
Fast, scalable simulation is key for us to meet the tight development schedules of our complex 28nm FD-SOI SoCs and ASICs for smart driving and industrial IoT. We measured 8X faster serial-mode DFT performance with the Cadence Xcelium Parallel Simulator, and selected it as the standard simulation solution...
Francois Oswald, CPU team manager, STMicroelectronics
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