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- Speeds up simulation using commonly available multi-core servers
- Supports large and complex jobs (more than one billion logic gates)
- Provides full debug visibility
Complementing compiled-code simulators, Cadence® RocketSim™ parallel simulation engine eliminates functional verification bottlenecks by speeding up simulation using commonly available multi-core servers. The engine is proven for register-transfer level (RTL) system on chip (SoC), gate-level functional simulation, and gate-level design for test (DFT) simulation in numerous marquee systems and semiconductor companies in the mobile, server, and graphics domains.
Ever-growing chip density and complexity slow down simulation, making functional verification a severe bottleneck. As a result, chip design projects miss their time-to-market targets, or designers end up taping out early with less confidence.
RocketSim parallel simulation engine solves the bottleneck common in existing compiled-code simulators by offloading the time-consuming calculations to an ultrafast multi-core engine. As a result, the engine achieves performance gains over compiled-code simulators of:
- Up to 6X for RTL SoC
- Up to 10X for gate-level functional simulation
- And up to 30X for gate-level DFT simulation
The engine also complements hardware-based accelerators by executing full four-state, bit-precise logic (0, 1, X, Z), and works from within the familiar simulator environment. Working seamlessly with Cadence Incisive® Enterprise Simulator, the RocketSim engine speeds up the simulation process without the need to modify designs or testbenches. The engine supports large and complex designs (over one billion gates) and provides full visibility of your design, including debug access. These capabilities help extend simulation to include larger designs and more complex tests.
Also available is the RocketSim-CPU, a co-simulator that runs on a standard multicore CPU server and dramatically accelerates a wide range of Verilog simulations. From an IT perspective, deployment of RocketSim-CPU is seamless as it does not require installation of any hardware.
RocketSim parallel simulation engine:
- Scales to available cores for performance
- Speeds up leading compiled code simulators
- Complies with IEEE 1364 Verilog, 1800 SystemVerilog (including SVA), 1076 VHDL
- Executes full support for four-state logic (0, 1, X, Z)
- Executes X-propagation support
- Runs alongside the testbench
- Supports UVM, OVM, eRM, and VMM testbenches
- Supports PLI/VPI compliant interface
- Enables direct dump of FSDB/SST2 waveforms
- Enables quick ramp-up
Before Design Automation Conference 2016, Deep Chip's John Cooley placed the RocketSim engine at the top of his "must-see" list for the show.
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