- Uses formal technology to add innovative functional verification for complex synchronizer protocols and metastability, enabling comprehensive CDC signoff
- Automatically infers CDC intent from the design and comprehensively analyzes structural, functional, and reconvergence issues
- Fully integrated with the powerful JasperGold Visualize debug environment, utilizing proven formal intelligence to reduce violation noise, speed debug, and improve waiver handling
Modern system-on-chip (SoC) designs typically contain multiple asynchronous clock domains, and signals are frequently transferred from one clock domain to another. In hardware, such clock domain crossing (CDC) signals are often subject to metastability effects that can cause functional failures Traditional methods like RTL simulation or static timing analysis alone are not sufficient to verify that the data is transferred consistently and reliably across clock domains. As a result, many CDC-related bugs go undetected until the post-silicon verification stage, necessitating costly re-spins.
The Cadence® JasperGold® Clock Domain Crossing (CDC) App enables users to perform comprehensive CDC signoff. It automatically infers CDC intent from the design and comprehensively analyzes structural, functional, and reconvergence issues. Fully integrated with the JasperGold Visualize™ debug environment, the App also provides advanced CDC-specific debugging options, with efficient violation- and waiver-handling capabilities.
- Strong functional checks backed by best-in-class formal engines
- Best-in-class integrated debug environment
- Metastability modeling and injection in both formal and simulation
- Automatic metastability fault sensitivity flow
- Flexible reporting system based on filters
- Tight integration with Xcelium™ Parallel Logic Simulation
- Auto/Safe waiver flow
“We’ve identified functional and structural CDC issues earlier in the RTL signoff phase using the JasperGold CDC App. Eliminating these bugs earlier in the process has increased the quality of our designs and saved us between two and four weeks on the design and verification time for each of our IP.”
David Vincenzoni Design Manager at STMicroelectronics