While “correct by construction” tools and techniques go a long way, errors can still creep in due to unclear or erroneous specifications, the addition of low-power structures, built-in self-test (BIST), and JTAG support, or downstream changes/engineering change orders (ECOs) that weren’t fully propagated. In addition, connectivity of a sub-module that appears correct may prove to be erroneous in a larger scope.
JasperGold Connectivity Verification App performs exhaustive verification in hours, not the days or weeks common for simulation-based approaches. Unlike competitive formal connectivity apps that output noisy, hard to read counterexamples (CEX), the app’s QuietTrace™ debug technology shows errors via “low-noise”, minimum-length CEX traces for high user productivity. Since creating the connectivity definition can be tedious and error-prone, the app can also extract connectivity from a golden RTL and verify any unintended changes in a subsequent RTL revision. The app is completely automated, so you won’t need to learn formal or SystemVerilog Assertions (SVAs).
- Supports all connectivity types: unconditional/static (i.e. basic "point-to-point"), constant and dynamic conditional, combinational value propagation without latencies, and sequential value propagation with latencies
- Captures the connectivity description in open, human, and machine-readable Excel/OpenOffice spreadsheets, comma-separated-values (CSV) files, or IP-XACT xml
- Includes a utility to quickly black-box out the internals of IP blocks so the verification only focuses on connectivity
- Makes it easy, once the connectivity description is set up, for you to fully automate this flow and run it in a regression mode
- Includes innovative reverse connectivity capability, enabling you to automatically create a high-level connectivity specification from your known-good design
- Supports parallelism with our ProofGrid formal engine control utility