- Verify compliance to standard protocols with exhaustive assertion-based verification IP libraries
- Enable automated, encapsulated, plug-and-play capabilities
- Provide quality support for spec-compliant designs
Optimized for high-performance execution and rapid debug, Assertion-based VIP consists of libraries of assertion-based verification intellectual property (IP) for exhaustively verifying the compliance of a design under test (DUT) to a given protocol. With our Assertion-based VIP, you can find critical bugs early on and shorten your overall verification schedule.
All of our Assertion-based VIP are optimized for high-performance execution in our formal engines and ProofGrid™ technologies, along with rapid debug with our unique QuietTrace™ technologies. The VIP also works with our unique Visualize™ capability for early integration of your implementation and the kit and/or rapid protocol customization/extension. The VIP includes reusable “Recipes” to explore protocol functionality and intent based on interface events. The protocol-related properties generated support early exploration and verification of protocol specifications, are optimized for formal, and plug seamlessly into the simulation environment.
In the case of ARM® protocols, all of Cadence’s ARM-related Assertion-based VIP products are ARM certified and optimized for high performance with our formal engines and debug workflow. Each VIP offering works with our JasperGold® Formal Property Verification App to formally prove the embedded properties. As a result, you won’t need to manually write properties. The VIP also works with many other JasperGold Apps. When an Assertion-based VIP is used with these apps, you can visualize protocol transactions and timing diagrams to understand behaviors of properties as well as design specifications via our Visualize technology.
- Using the Assertion-based VIP with the JasperGold Formal Property Verification App eases debugging thanks to powerful Visualize technology that displays “live” interesting waveforms. If a counter-example is found, constraints can be added or modified on-the-fly using Visualize technology.
- QuietTrace technology simplifies the debug process even further, calculating the minimum signal activity needed to describe the behavior in question. This greatly accelerates your exploration and debugging tasks.
- Assertion-based VIP products are easy to adjust to support cases where you are tailoring and/or only implementing a subset of a given protocol
- All Assertion-based VIP products include reusable “Recipes” to explore protocol functionality and intent based on interface events
- The Assertion-based VIP properties are written in standard IEEE SystemVerilog Assertions (SVA) and are optimized for runtime and memory performance with our formal engines