Delivering Shortest Turnaround Time and Predictable Quality
As electronic products across all market segments become more sophisticated, developing their underlying hardware and software, and integrating the two sides, continues to grow more complex. Early software development, hardware verification, hardware/software integration, and integrated system validation have become primary challenges, increasing development costs, project schedules, and risks.
Using the Cadence® System Development Suite, you can reduce system integration time by up to 50%, accelerating intellectual property (IP) development, system-on-chip (SoC) integration, and concurrent hardware/software development. This verification suite is comprised of core engines, verification fabric technologies, and solutions spanning these technologies, as shown in Figure 1.
Core engines include JasperGold® formal verification, RocketSim™ and Incisive® simulation, Palladium® emulation, and Protium™ FPGA prototyping. We developed each engine to provide best-in-class technology.
Verification fabric technologies include Verification IP, Incisive vManager™ planning and metrics, Indago™ debug solutions, and Perspec™ software-driven testing. We developed these technologies to provide a flow-driven multi-engine verification environment.
Solutions in the suite include total throughput for the shortest project schedule, metric-driven signoff for quality, and an application-centric focus to meet the needs of products for mobile, networking and servers, automotive, consumer and the Internet of Things (IoT), aerospace and defense, and other vertical segments.
Our System Development Suite technologies, flows, and solutions support a broad range of industry standards, are open for third-party integration, and are further augmented by our ecosystem partners, including ARM and many others.
The Palladium Z1 platform uniquely met our requirements due to its reliability as a datacenter compute resource, offering advanced multi-user capabilities and scalability from small four-million-gate verification payloads to multi-billion gate designs.
Daniel Diao, Deputy General Manager of the Turing Processor Business Unit, Huawei
The ability to use the same bring-up flow for Palladium emulation and Protium rapid prototyping allows our design teams to switch seamlessly between the two execution engines, which reduces the prototype bring-up time from months to weeks.
Hideya Sato, Deputy Executive GM, Hitachi, LTD
The Incisive vManager solution has been very well accepted by our design and verification teams because it’s really straightforward, intuitive, and easy to use. The Incisive vManager solution helps us with project visibility, which improves our verification productivity.
Mirella Negro Marcigaglia, Verification Manager, STMicroelectronics