SoC Test Generation
with Perspec System Verifier
Supporting portable stimulus
specification 1.0 across the
Cadence Verification Suite
Achieve Dramatic Speed Up in Logic Simulation with Cadence Xcelium, the First Truly Parallel Logic Simulator and Cut FPGA-Based Prototyping Time with Protium S1
Protium S1 Platform
Reduce FPGA-based prototype
bring-up from months to days
Industry's first production-proven multi-core simulator
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System Design and Verification Flows
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Emulation
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Debug Analysis
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Formal and Static Verification
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FPGA-Based Prototyping
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Planning and Management
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Simulation and Testbench Verification
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Software-Driven Verification
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Verification IP
Technology Leadership with the Cadence Verification Suite
Over the past decade, verification complexity and demands on engineering teams have continued to rise rapidly. Applying innovative solution flows, automation tools, and best-in-class verification engines is necessary to overcome the resulting verification gap.
The Cadence® Verification Suite combines the market- and technology-leading JasperGold® Formal Verification Platform, Palladium® Z1 Enterprise Emulation, the Xcelium™ Parallel Simulator, and the Protium™ S1 FPGA-Based Prototyping Platform with fabric technologies across the core engines.
Delivering Shortest Turnaround Time and Predictable Quality
As electronic products across all market segments become more sophisticated, developing their underlying hardware and software—and integrating the two sides—continues to grow more complex. Early software development, hardware verification, hardware/software integration, and integrated system validation have become primary challenges, increasing development costs, project schedules, and risks.
Using the Cadence Verification Suite, you can reduce system integration time by up to 50%, accelerating IP development, system-on-chip (SoC) integration, and concurrent hardware/software development. The verification suite is comprised of core engines, verification fabric technologies, and solutions spanning these technologies, as shown in Figure 1.
Core engines, each developed to provide best-in-class technology, include:
- Formal: JasperGold Formal Verification Platform
- Simulation: Xcelium Parallel Logic Simulator, Specman® Elite
- Emulation: Palladium Z1 Enterprise Emulation Platform
- FPGA Prototyping: Protium S1 FPGA-Based Prototyping Platform
The verification fabric provides automation, debug, tracking, management, and measurement of verification tasks across verification flows and engines, which improves productivity and increases team collaboration and productivity.
Verification fabric technologies include:
- Protocol verification: Verification IP
- Metric-driven verification: vManager™ Metric-Driven Signoff Platform
- Design and verification debug: Indago™ Debug Platform
- Portable use-case stimulus: Perspec™ System Verifier
Solutions in the Verification Suite are predefined flows and best practices to address common challenges, including total throughput for the shortest project schedule, metric-driven signoff for quality, and application-specific challenges for mobile, networking and servers, automotive, consumer and internet of things (IoT), aerospace and defense, and other vertical segments.
Our Verification Suite engines, fabric technologies, and solutions support a broad range of industry standards, are open for third-party integration, and are further augmented by our ecosystem partners, including Arm and many others.
Resource Library VIEW ALL
Video (141)
- HPE Apollo 70 Collaboration
- The Cadence vManager Metric-Driven Signoff Platform in Use at NXP
- Specman: Fastest Patches on Earth
- Orit Kirshenberg - Expert Insights Video
- Big FPGA Boards for ASIC Prototyping
- Case Studies for Successful FPGA Based Prototyping
- Hardware Solutions for FPGA-based Prototyping
- Hardware Solutions for FPGA-Based Prototyping
- Emulating a Dual-Port 10G/40G NIC on Palladium and RPP
- Hitachi: Faster Bring Up with Protium Platform
- Bluespec Taps Into Rapid Prototyping Platform for Hybrid Prototyping
- Faster HW/SW Debug, Embedded Software Development and System Validation
- Protium S1 used to prototype a pedestrian detection application.
- New Cadence Products Expand the Verification Suite: Xcelium Parallel Simulator and Protium S1 Platform
- Firmware Development and Pre-silicon Verification with FPGA-based Prototyping
- FPGA Prototyping Enables Rapid Development of Customizable Processors
- FPGA-Prototyping of an Automotive Ethernet based Parking Assist System
- Reduce FPGA-Based Prototype Bring-Up From Months to Days with Cadence Protium S1 Platform
- UVM Multi-language with e, SystemVerilog, SystemC, C/C++
- Nadav Eden – Specman Expert Insights Video
- Yoav Lurie—Specman Expert Insights Video
- Extoll - Dr. Niels Burkhardt—Specman Expert Insights video
- New Key Features of Xcelium for Advanced Mixed-Signal Verification
- The People Behind Range Generated Field (RGF) - Specman 18.03
- Mike Bartley, CEO of T&VS, on Portable Stimulus
- Car window anti-trap protection with the Cadence Zynq-7000 Virtual Platform
- AMIQ Eclipse IDE for Perspec Portable Stimulus
- ST Optimizes Verification Across the Globe with the vManager Platform
- MultiPhy Verifies Diverse Blocks Quickly with Specman + MATLAB Flow
- Get Great Results with JasperGold CDC
- The Benefits of Running the Xcelium Parallel Logic Simulator on Cavium’s Arm Based ThunderX2
- Latest News for Cadence Specman Elite - January 2018
- Using the Cadence VirtualBridge Emulator with the Palladium Platform
- Taking FPGA-Based Prototyping to the Next Level
- DAC 2017 Report on Accellera Portable Stimulus Specification
- Accellera Portable Stimulus Standard Introduction and Demo; Part 1 of 3 – Introduction
- Accellera Portable Stimulus Standard Introduction and Demo; Part 3 of 3 - Conclusions
- Accellera Portable Stimulus Standard Introduction and Demo; Part 2 of 3 – The Demo
- Xcelium Parallel Simulator on Cavium Arm-based ThunderX2
- CDNLive India – A Closer Look at State-of-the-Art Verification Techniques and Methodologies
- New JasperGold platform for Advanced RTL Signoff
- Achieve Dramatic Speed-Up in Logic Simulation with Xcelium Parallel Simulator
- Pedestrian Detection: Cadence Tensilica IVP DSP on Cadence Protium FPGA-based prototyping platform
- Augmenting Simulation Via Low-Power Verification Methodologies with Emulation
- Imperas Software - Cadence System Development Suite
- Finding Difficult Bugs Early Via Emulation
- Low-Power Mixed-Signal Verification of Freescale Kinetis Products
- Verification Solutions for ARM v7/v8 Based Systems on Chip
- Imagination - The Ten Myths about Formal
- UVM methodology based Verification Environment for Imaging IPs/SoCs
- IBM - Cadence Functional Verification for Improved Planning and Schedule Adherence
- Closing Gaps in Mixed-Signal Power Implementation Using a Consistent Power Intent
- Accelerate Your Verification Debug with the Incisive Debug Analyzer
- Texas Instruments - Highly Scalable Multicore ARM A15 Verification with Specman/e
- DVCon 2013 Best Practices in Verification Planning
- How Real Number Modeling Improves Functional Verification for Mixed-Signal SoCs
- Faster Debugging with X-Propagation Simulation and SimVision Debug Capabilities in Incisive Platform
- NXP Shortens Verification Cycle for Smart Card SoC
- Formal Methodology as a 1st Step in Verification Shortens Process by 4 Weeks
- Freescale Tracks Thousands of Simulations Before Tapeout for Bug-Free Silicon
- Fast Debug of RTL, Speedy Post Analysis
- Detecting Low-Power Bugs with X-Optimism Simulation
- Detecting System-Level Corner Cases During Low-Power SoC Verification
- Faster HW/SW Verification and Bring-up with Hybrid Virtual Platform
- Tapping Into UVM-ML to Support Reuse in Multi-Language Verification Environment
- PMC Expert Insights video
- Cadence Functional Safety Solution
- Metric-Driven Verification: A Look at How this Methodology Accelerates Verification Process
- Low Power Verification USING CPF/IEEE 1801 and Application of Formal Verification at Chip Level
- Best Practices in Verification Planning
- Tuning Your UVM Environment for Maximum Performance
- Speed Verification Turnaround by Extending MDV to TLM
- National and Cadence Building a More Efficient Chip Design Flow
- Verifying Freescale's 64-bit Core with Rapid Prototyping Tools
- Plan-Driven Low-Power Verification and Debugging at STMicroelectronics
- Testing The Testbench
- UVM-Acceleration, Assertions and Coverage demo
- UVM SystemVerilog in a Multi-Language SoC World
- Connecting SystemVerilog Real Numbers and Verilog-AMS Nets
- Cadence Palladium for SoC Performance Validation and Analysis
- Better Verification Performance with Incisive Enterprise Simulator
- System Level Low Power Verification Using Palladium and CPF
- Broadcom Faster System Bring Up with an Embedded Test Bench on Palladium
- Contemporary Verification Consultants e-asing your verification pains with IEEE 1647 & IES
- Freescale Best Practice in Verification Planning
- A Look at Cadence System Development Tools
- 5 Steps to Your First Power Shut-off (PSO) Verification
- MediaTek Gets High-Quality Smart Devices to Market Quickly with Palladium Platform
- Easing Embedded Software Development for Complex SOCs
- Xilinx - Cadence Virtual Processing Platform and Zynq-7000
- Increased Trace Depth, Faster Upload and Time to Market for Zenverge
- Freescale Closes Coverage Gap in SoC Environments with Palladium XP Platform
- Open-Source UVM Multilanguage Architecture Simplifies Verification IP Reuse
- Allegro Microsystems Improves Efficiency and Productivity with Incisive vManager Solution
- Xilinx - Cadence Virtual System Platform to Accelerate Product Development
- Validating Mobile SoC Architecture at Broadcom
- Enabling Verification of Complex System Scenarios Using Perspec System Verifer
- Palladium Z1: Advanced Job Re-shaping
- Verify Smarter with Industry's First Datacenter-Class Emulation System
- Emulating Nvidia GPUs
- Low-Power Verification Using Conformal Low-Power
- Accurate Low Power verification on a Complex Low Power Design using CLP
- SoC Static Power Verification with Encounter Conformal Low Power
- Cadence Perspec System Verifier SW Driven SoC Verification Automation
- Achieving Fast Formal Verification in Highly Configurable Design Environment
- NVIDIA Handles Complexity with Palladium Z1 Platform
- Introducing the Palladium Z1 Enterprise Emulation Platform
- AMD - Cadence Palladium XP & In-Circuit Acceleration
- Cadence Functional Safety Solution for Automotive Design
- Faster Simulation, Faster Builds at Freescale with Palladium XP Platform
- LPDDR4 IP Verification Challenges
- PMC - Power Estimation – An Evolving Science
- Design Challenges in Developing Sub-Volt IP Designs for IoT Applications
- Introducing Low-power Verification RAK
- Is End-to-End Formal Complete?
- JasperGold Formal Apps for Design Bring-up
- Next-Generation JasperGold Formal Verification Platform
- X-FAB Revamps Low-Power Design Flow with CPF
- Leveraging SystemVerilog Real Number Modeling
- DAC 2012: Interview with Dr. Kerstin Eder about her course on functional verification
- Shorten Verification Time with Specman
- Methods2Business Creates MAC Layers Without Compromising on Verification with C-to-Silicon Compiler
- NVIDIA - Palladium/VSP ARM v8 Tegra Hybrid
- Dialog Semiconductor Verifies Register Map Overnight with Cadence RegVal Formal App
- Using SystemC and HLS to Evaluate Co-Processor Architectures
- Leveraging a System-C Based Design Flow
- Pre and Post Silicon Verification: The Best of Both Worlds
- Using Palladium Platform to Exhaustively Verify a Configurable Coherent NoC IP
- Delivering High Quality Denver IP Utilizing IP Acceleration
- High-Level Synthesis: a Winning Technology
- One Metric to Rule Them All? Tracking Progress on Formal Testbenches
- Using Palladium/VSP Hybrid to Accelerate SW Development
- Freescale - Palladium XP helps speed their verification effort by 10,000x over simulation
- Reducing Time to Point of Interest with Accelerated OS Boot
- Experiences with SoC Deployment of Hardware Emulation Based Power Intent Modeling
- See How Nvidia Boosts IP Acceleration of Custom ARM Core
- Incisive vManager Solution - Experience the Difference
- Get Your Weekends Back with Faster Chip Verification Process
- Dancing Robots! @CDNLive EMEA 2014
- Palladium XP Introduction
- In-Circuit Acceleration Demo Full Version
Datasheet (40)
- Perspec System Verifier Datasheet
- SpeedBridge Adapter for USB 3.0/2.0/1.1 Devices
- SpeedBridge Adapter for PCIe 4.0 Datasheet
- VirtualBridge Adapter for PCI Express 2.0/3.0 Datasheet
- Xcelium Parallel Logic Simulation Datasheet
- Protium S1 Single-FPGA Board Datasheet
- Protium S1 FPGA-Based Prototyping Platform Datasheet
- vManager Metric-Driven Signoff Platform Datasheet
- Emulation Development Kit for Palladium Series Datasheet
- Memory Model Portfolio for Palladium Series Datasheet
- Virtual JTAG Virtual JTAG Debug Interface Datasheet
- Palladium Z1 Enterprise Emulation Platform Datasheet
- Embedded Software Debug App Datasheet
- Incisive Functional Safety Simulator Datasheet
- Cadence SpeedBridge Adapter for USB 2.0 Host Datasheet
- Cadence SpeedBridge Adapter for PCI Express 3.0 Datasheet
- Stratus High-Level Synthesis Datasheet
- Cadence SpeedBridge Adapter for Serial ATA (SATA) Datasheet
- SpeedBridge Adapter for USB 3.0 Devices Datasheet
- Protium FPGA-Based Prototyping Platform Datasheet
- Cynthesizer Solution Datasheet
- Cadence SpeedBridge Adapter for Ethernet Datasheet
- Incisive Verification Apps Datasheet
- Metric-Driven Mixed-Signal Verification Flow Datasheet
- Cadence Accelerated Verification IP for PCI Express Datasheet
- Cadence Virtual System Platform for the Xilinx Zynq-7000 All Programmable SoC Datasheet
- Incisive Enterprise Verifier Datasheet
- Incisive Enterprise Simulator Datasheet
- Cadence SpeedBridge Adapter for ARM Logic Tiles Datasheet
- Cadence Palladium Dynamic Power Analysis Datasheet
- Cadence Virtual System Platform Datasheet
- Cadence SpeedBridge Adapter for Serial-Attached SCSI (SAS) Datasheet
- Cadence SpeedBridge System for Video and Audio Datasheet
- Cadence Incisive SpeedBridge Adapter for PCI Express 2.0 Datasheet
- Cadence SpeedBridge Adapter for PCI Express Datasheet
- Incisive Assertion-Based Verification IP (ABVIP) for OCP Datasheet
- Incisive Formal Verifier Datasheet
White Paper (21)
- Delivering Superior Throughput for EDA Verification Workloads White Paper
- Three Things You Need to Know to Use the Accellera PSS White Paper
- Efficient Verification of Mixed-Signal SerDes IP Using UVM
- Choosing the Right Verification Technology for CDC-Clean RTL Signoff
- Choosing the Right Superlinting Technology for Early RTL Code Signoff White Paper
- A Program Manager’s Guide to Successful Integrated Circuit Verification
- Massive SoC Designs Open Doors to New Era in Simulation White Paper
- SoC Planning, Management, Reporting, Auditing, and Signoff White Paper
- Improving Emulation Throughput for Multi-Project SoC Designs White Paper
- Gate-Level Simulation Methodology White Paper
- Automating Root-Cause Analysis to Reduce Time to Find Bugs by Up to 50% White Paper
- Meeting Functional Safety Requirements Efficiently Via Electronic Design Tools and Techniques White Paper
- How the Productivity Advantages of High-Level Synthesis Can Improve IP Design, Verification, and Reuse White Paper
- Enabling ISO 26262 Qualification By Using Cadence Tools White Paper
- A Better Tool for Functional Verification of Low-Power Designs with IEEE 1801 UPF White Paper
- Maximizing Verification Effectiveness Using Metric-Driven Verification White Paper
- Analyzing and Debugging Performance Issues with Advanced ARM CoreLink System IP Components White Paper
- Productivity, Predictability, and Use-Model Versatility: The Three Key Care-Abouts of Choosing Hardware-Assisted Verification White Paper
- Building Energy-Efficient ICs from the Ground Up White Paper
- Solutions for Mixed-Signal SoC Verification White Paper
- Interface Additions to the e Language for Effective Communication with SystemC TLM 2.0 Models White Paper
Success Story Video (6)
- UVM methodology based Verification Environment for Imaging IPs/SoCs
- Plan-Driven Low-Power Verification and Debugging at STMicroelectronics
- NVIDIA Handles Complexity with Palladium Z1 Platform
- Introducing the Palladium Z1 Enterprise Emulation Platform
- AMD - Cadence Palladium XP & In-Circuit Acceleration
- Shorten Verification Time with Specman
Technical Brief (4)
Press Releases (42)
- Cadence Verification Suite Enabled on Arm-Based HPC Datacenters
- Cadence Accelerates Arm-Based Server Development by Automating Arm Pre-Silicon Bare Metal Compliance Testing
- Cadence Palladium Z1 Enterprise Emulation Platform Enables GUC to Accelerate SoC Design
- Cadence JasperGold Formal Verification Platform Enables Hitachi to Develop Measures for Fault Avoidance to Comply with IEC 61508 Series SIL 4 Requirements
- Cadence Perspec System Verifier Supports New Accellera Portable Test and Stimulus Specification 1.0
- Cadence Full-Flow Digital and Signoff Tools and Verification Suite Provide Optimal Results for 7nm Arm Cortex-A76 CPU Designs
- Media Alert: Cadence to Showcase Verification Suite at DVCon 2018
- Cadence and Arm Deliver First SoC Verification Solution for Low-Power, High-Performance Arm-Based Servers
- Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
- Hiroshima University Research Team Accelerates the Development of a Computer-Aided Medical Diagnosis System with Cadence Tensilica Vision P6 DSP Core and Protium S1 FPGA-Based Prototyping Platform
- Teradyne Standardizes on Cadence Xcelium Parallel Logic Simulator
- Cadence Announces VirtualBridge Adapter for Palladium Z1 Emulator to Accelerate Software Bring-Up Time by Up to Three Months
- Cadence Expands JasperGold Platform for Advanced Formal-Based RTL Signoff
- Amlogic Reduces HW/SW Integration Time for Multimedia SoCs by Two Months Using the Cadence Protium S1 FPGA-Based Prototyping Platform
- Renesas Accelerates IoT Design Using the Cadence Perspec System Verifier
- Cadence Launches Protium S1 FPGA-Based Prototyping Platform for Early Software Development
- Cadence Launches Xcelium Parallel Simulator, the Industry’s First Production-Proven Parallel Simulator
- Fujitsu Adopts Cadence Palladium Z1 Enterprise Emulation Platform for Post-K Supercomputer Development
- Cadence Completes Acquisition of Rocketick Technologies
- Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow
- Cadence Ushers in New Era of Datacenter-class Emulation with Palladium Z1 Enterprise Emulation Platform
- Altair Semiconductor Adopts Cadence Palladium XP Platform for Advanced IoT SoC Development
- Realtek Accelerates System-on-Chip Verification with Cadence Palladium XP Platform
- Cadence Announces Next-Generation JasperGold Formal Verification Platform
- Cadence Introduces Indago Debug Platform, Improving Debugging Productivity by up to 50 Percent
- Media Alert: Cadence to Showcase System Design and Verification Solutions at DVCon US 2015
- M31 Technology Adopts Cadence Verification IP to Achieve 2.5X Faster Verification
- DMP Adopts Cadence Palladium XP Platform to Accelerate High Performance Graphic IP Core Development
- Cadence Perspec System Verifier Delivers Up to 10X Productivity Improvement in System-on-Chip Verification
- Sonics Adopts Cadence JasperGold Apps Formal Verification for On-Chip Network IP Development
- Cadence Introduces Automotive Functional Safety Verification Solution, Reducing ISO 26262 Compliance Preparation Effort by up to 50 Percent
- Cadence Announces Protium Rapid Prototyping Platform and Expands System Development Suite Low-Power Verification
- Cadence Completes Acquisition of Jasper Design Automation
- CSR Selects Cadence Palladium XP Platform for Development of ARM-based Automotive Infotainment Systems
- HiSilicon Expands Cadence Palladium XP Platform Usage For Mobile and Digital Media SoC and ASIC Development
- Cadence Incisive Specman Elite Testbench Reduces Verification Time for Sharp by 50 Percent
- Cadence Expands ARM-based System Verification Solution, Reducing Time-to-Market for Mobile, Networking and Server Applications
- Cadence Redefines Verification Planning and Management with Incisive vManager Solution
- Cadence Incisive 13.2 Platform Sets New Standard for SoC Verification Performance and Productivity
- Ricoh Selects Cadence Palladium XP Platform for Next-Generation Multifunction Printer SoC Development
- New Release of Cadence Incisive Platform Doubles Productivity of SoC Verification
- Cadence Virtual System Platform Named as American Technology Award Finalist in Software Category
Customers Success (22)
- Renesas Deploys Cadence Interconnect Workbench with Palladium Z1 Platform
- Cadence and NetSpeed Success Story
- Moving to UVM-MS to Meet Coverage Goals Case Study
- Faster Hardware Verification and Software Validation for Supercomputers Success Story
- Cadence and Ricoh Success Story
- Cadence and VIA Telecom Success Story
- Cadence and Faraday Technology Case Study
- Cadence and STMicroelectronics Success Story
- Cadence and Melexis Success Story
- Cadence and STMicroelectronics Success Story
- Cadence and RivieraWaves Success Story
- Cadence and Siemens Healthcare Success Story
- Texas Instruments and Cadence Verification Success Story
- Cadence and Nufront Success Story
- Cadence Incisive Enterprise Simulator and Samsung Success Story
- Cadence and Samsung Success Story
- Cadence and STMicroelectronics Success Story
- Cadence and QLogic Success Story
- Cadence and Xilinx Success Story
- Cadence and Texas Instruments Success Story
- Cadence and Newport Media Success Story
- Cadence and UPEK Success Story
Webinar (20)
- Protium FPGA-Based Prototyping Platform
- Augmenting Simulation Via Low-Power Verification Methodologies with Emulation
- Why Debug at Signal Level
- Accelerate Your Verification Debug with the Incisive Debug Analyzer
- Metric-Driven Verification: A Look at How this Methodology Accelerates Verification Process
- Best Practices in Verification Planning
- Tuning Your UVM Environment for Maximum Performance
- Speed Verification Turnaround by Extending MDV to TLM
- What to Do When Code Coverage Closure Seems Impossible
- Optimizing Your Verification Process with Incisive vManager
- Verification Techniques with Assertion-Based VIP
- UVM SystemVerilog in a Multi-Language SoC World
- Introducing UVM Multi-Language Open Architecture
- Formal Apps to Automate Mainstream Verification Challenges
- Connecting SystemVerilog Real Numbers and Verilog-AMS Nets
- Better Verification Performance with Incisive Enterprise Simulator
- 5 Steps to Your First Power Shut-off (PSO) Verification
- Leveraging SystemVerilog Real Number Modeling
- SimVision Simplifies UVM SystemVerilog Macro Debug
- Simplify UVM Debug with Cadence Incisive SimVision
Demo (5)
- FPGA-Prototyping of an Automotive Ethernet based Parking Assist System
- Accellera Portable Stimulus Standard Introduction and Demo; Part 1 of 3 – Introduction
- Accellera Portable Stimulus Standard Introduction and Demo; Part 3 of 3 - Conclusions
- Accellera Portable Stimulus Standard Introduction and Demo; Part 2 of 3 – The Demo
- Xcelium Parallel Simulator on Cavium Arm-based ThunderX2
Customers
The Palladium Z1 platform uniquely met our requirements due to its reliability as a datacenter compute resource, offering advanced multi-user capabilities and scalability from small four-million-gate verification payloads to multi-billion gate designs.
Daniel Diao, Deputy General Manager of the Turing Processor Business Unit, Huawei
The ability to use the same bring-up flow for Palladium emulation and Protium rapid prototyping allows our design teams to switch seamlessly between the two execution engines, which reduces the prototype bring-up time from months to weeks.
Hideya Sato, Deputy Executive GM, Hitachi, LTD
The Incisive vManager solution has been very well accepted by our design and verification teams because it’s really straightforward, intuitive, and easy to use. The Incisive vManager solution helps us with project visibility, which improves our verification productivity.
Mirella Negro Marcigaglia, Verification Manager, STMicroelectronics
Cadence Verification Suite Products A-Z
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