Achieve Dramatic Speed Up in Logic Simulation with Cadence Xcelium, the First Truly Parallel Logic Simulator and Cut FPGA-Based Prototyping Time with Protium S1
Protium S1 Platform
Reduce FPGA-based prototype
bring-up from months to days
Industry's first production-proven multi-core simulator
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System Design and Verification Flows
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Emulation
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Debug Analysis
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Formal and Static Verification
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FPGA-Based Prototyping
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Planning and Management
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Simulation and Testbench Verification
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Software-Driven Verification
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Verification IP
Technology Leadership with the Cadence Verification Suite
Over the past decade, verification complexity and demands on engineering teams have continued to rise rapidly. Applying innovative solution flows, automation tools, and best-in-class verification engines is necessary to overcome the resulting verification gap.
The Cadence® Verification Suite combines the market- and technology-leading JasperGold® Formal Verification Platform, Palladium® Z1 Enterprise Emulation, the Xcelium™ Parallel Simulator, and the Protium™ S1 FPGA-Based Prototyping Platform with fabric technologies across the core engines.
Delivering Shortest Turnaround Time and Predictable Quality
As electronic products across all market segments become more sophisticated, developing their underlying hardware and software—and integrating the two sides—continues to grow more complex. Early software development, hardware verification, hardware/software integration, and integrated system validation have become primary challenges, increasing development costs, project schedules, and risks.
Using the Cadence Verification Suite, you can reduce system integration time by up to 50%, accelerating IP development, system-on-chip (SoC) integration, and concurrent hardware/software development. The verification suite is comprised of core engines, verification fabric technologies, and solutions spanning these technologies, as shown in Figure 1.
Core engines, each developed to provide best-in-class technology, include:
- Formal: JasperGold Formal Verification Platform
- Simulation: Xcelium Parallel Logic Simulator, Specman® Elite
- Emulation: Palladium Z1 Enterprise Emulation Platform
- FPGA Prototyping: Protium S1 FPGA-Based Prototyping Platform
The verification fabric provides automation, debug, tracking, management, and measurement of verification tasks across verification flows and engines, which improves productivity and increases team collaboration and productivity.
Verification fabric technologies include:
- Protocol verification: Verification IP
- Metric-driven verification: vManager™ Metric-Driven Signoff Platform
- Design and verification debug: Indago™ Debug Platform
- Portable use-case stimulus: Perspec™ System Verifier
Solutions in the Verification Suite are predefined flows and best practices to address common challenges, including total throughput for the shortest project schedule, metric-driven signoff for quality, and application-specific challenges for mobile, networking and servers, automotive, consumer and internet of things (IoT), aerospace and defense, and other vertical segments.
Our Verification Suite engines, fabric technologies, and solutions support a broad range of industry standards, are open for third-party integration, and are further augmented by our ecosystem partners, including Arm and many others.
Datasheet (36)
- Perspec System Verifier Datasheet
- SpeedBridge Adapter for USB 3.0/2.0/1.1 Devices
- SpeedBridge Adapter for PCIe 4.0 Datasheet
- VirtualBridge Adapter for PCI Express 2.0/3.0 Datasheet
- Xcelium Parallel Logic Simulation Datasheet
- Protium S1 Single-FPGA Board Datasheet
- Protium S1 FPGA-Based Prototyping Platform Datasheet
- vManager Metric-Driven Signoff Platform Datasheet
- Palladium Z1 Enterprise Emulation Platform Datasheet
- Emulation Development Kit for Palladium Series Datasheet
- Memory Model Portfolio for Palladium Series Datasheet
- Virtual JTAG Virtual JTAG Debug Interface Datasheet
- Embedded Software Debug App Datasheet
- Incisive Functional Safety Simulator Datasheet
- Cadence SpeedBridge Adapter for USB 2.0 Host Datasheet
- Cadence SpeedBridge Adapter for PCI Express 3.0 Datasheet
- Cadence SpeedBridge Adapter for Serial ATA (SATA) Datasheet
- SpeedBridge Adapter for USB 3.0 Devices Datasheet
- Protium FPGA-Based Prototyping Platform Datasheet
- Cadence SpeedBridge Adapter for Ethernet Datasheet
- Incisive Verification Apps Datasheet
- Metric-Driven Mixed-Signal Verification Flow Datasheet
- Cadence Accelerated Verification IP for PCI Express Datasheet
- Cadence Virtual System Platform for the Xilinx Zynq-7000 All Programmable SoC Datasheet
- Incisive Enterprise Verifier Datasheet
- Incisive Enterprise Simulator Datasheet
- Cadence SpeedBridge Adapter for ARM Logic Tiles Datasheet
- Cadence Palladium Dynamic Power Analysis Datasheet
- Cadence SpeedBridge Adapter for Serial-Attached SCSI (SAS) Datasheet
- Cadence SpeedBridge System for Video and Audio Datasheet
- Cadence Incisive SpeedBridge Adapter for PCI Express 2.0 Datasheet
- Cadence SpeedBridge Adapter for PCI Express Datasheet
- Incisive Formal Verifier Datasheet
Customers Success (18)
- Moving to UVM-MS to Meet Coverage Goals Case Study
- Faster Hardware Verification and Software Validation for Supercomputers Success Story
- Cadence and Ricoh Success Story
- Cadence and STMicroelectronics Success Story
- Cadence and Melexis Success Story
- Cadence and STMicroelectronics Success Story
- Cadence and RivieraWaves Success Story
- Cadence and Siemens Healthcare Success Story
- Texas Instruments and Cadence Verification Success Story
- Cadence and Nufront Success Story
- Cadence Incisive Enterprise Simulator and Samsung Success Story
- Cadence and Samsung Success Story
- Cadence and STMicroelectronics Success Story
- Cadence and QLogic Success Story
- Cadence and Xilinx Success Story
- Cadence and Texas Instruments Success Story
- Cadence and Newport Media Success Story
- Cadence and UPEK Success Story
White Paper (14)
- Three Things You Need to Know to Use the Accellera PSS White Paper
- Efficient Verification of Mixed-Signal SerDes IP Using UVM
- Choosing the Right Verification Technology for CDC-Clean RTL Signoff
- Choosing the Right Superlinting Technology for Early RTL Code Signoff White Paper
- A Program Manager’s Guide to Successful Integrated Circuit Verification
- SoC Planning, Management, Reporting, Auditing, and Signoff White Paper
- Improving Emulation Throughput for Multi-Project SoC Designs White Paper
- Gate-Level Simulation Methodology White Paper
- Automating Root-Cause Analysis to Reduce Time to Find Bugs by Up to 50% White Paper
- Meeting Functional Safety Requirements Efficiently Via Electronic Design Tools and Techniques White Paper
- Enabling ISO 26262 Qualification By Using Cadence Tools White Paper
- Maximizing Verification Effectiveness Using Metric-Driven Verification White Paper
- Productivity, Predictability, and Use-Model Versatility: The Three Key Care-Abouts of Choosing Hardware-Assisted Verification White Paper
- Interface Additions to the e Language for Effective Communication with SystemC TLM 2.0 Models White Paper
Demo (4)
- Accellera Portable Stimulus Standard Introduction and Demo; Part 1 of 3 – Introduction
- Accellera Portable Stimulus Standard Introduction and Demo; Part 3 of 3 - Conclusions
- Accellera Portable Stimulus Standard Introduction and Demo; Part 2 of 3 – The Demo
- FPGA-Prototyping of an Automotive Ethernet based Parking Assist System
Press Releases (34)
- Cadence and Arm Deliver First SoC Verification Solution for Low-Power, High-Performance Arm-Based Servers
- Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
- Hiroshima University Research Team Accelerates the Development of a Computer-Aided Medical Diagnosis System with Cadence Tensilica Vision P6 DSP Core and Protium S1 FPGA-Based Prototyping Platform
- Teradyne Standardizes on Cadence Xcelium Parallel Logic Simulator
- Cadence Announces VirtualBridge Adapter for Palladium Z1 Emulator to Accelerate Software Bring-Up Time by Up to Three Months
- Cadence Expands JasperGold Platform for Advanced Formal-Based RTL Signoff
- Amlogic Reduces HW/SW Integration Time for Multimedia SoCs by Two Months Using the Cadence Protium S1 FPGA-Based Prototyping Platform
- Renesas Accelerates IoT Design Using the Cadence Perspec System Verifier
- Cadence Launches Protium S1 FPGA-Based Prototyping Platform for Early Software Development
- Cadence Launches Xcelium Parallel Simulator, the Industry’s First Production-Proven Parallel Simulator
- Fujitsu Adopts Cadence Palladium Z1 Enterprise Emulation Platform for Post-K Supercomputer Development
- Cadence Completes Acquisition of Rocketick Technologies
- Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow
- Cadence Ushers in New Era of Datacenter-class Emulation with Palladium Z1 Enterprise Emulation Platform
- Altair Semiconductor Adopts Cadence Palladium XP Platform for Advanced IoT SoC Development
- Realtek Accelerates System-on-Chip Verification with Cadence Palladium XP Platform
- Cadence Announces Next-Generation JasperGold Formal Verification Platform
- Cadence Introduces Indago Debug Platform, Improving Debugging Productivity by up to 50 Percent
- Media Alert: Cadence to Showcase System Design and Verification Solutions at DVCon US 2015
- M31 Technology Adopts Cadence Verification IP to Achieve 2.5X Faster Verification
- DMP Adopts Cadence Palladium XP Platform to Accelerate High Performance Graphic IP Core Development
- Cadence Perspec System Verifier Delivers Up to 10X Productivity Improvement in System-on-Chip Verification
- Cadence Introduces Automotive Functional Safety Verification Solution, Reducing ISO 26262 Compliance Preparation Effort by up to 50 Percent
- Cadence Announces Protium Rapid Prototyping Platform and Expands System Development Suite Low-Power Verification
- Cadence Completes Acquisition of Jasper Design Automation
- CSR Selects Cadence Palladium XP Platform for Development of ARM-based Automotive Infotainment Systems
- HiSilicon Expands Cadence Palladium XP Platform Usage For Mobile and Digital Media SoC and ASIC Development
- Cadence Incisive Specman Elite Testbench Reduces Verification Time for Sharp by 50 Percent
- Cadence Expands ARM-based System Verification Solution, Reducing Time-to-Market for Mobile, Networking and Server Applications
- Cadence Redefines Verification Planning and Management with Incisive vManager Solution
- Cadence Incisive 13.2 Platform Sets New Standard for SoC Verification Performance and Productivity
- Ricoh Selects Cadence Palladium XP Platform for Next-Generation Multifunction Printer SoC Development
- New Release of Cadence Incisive Platform Doubles Productivity of SoC Verification
- Cadence Virtual System Platform Named as American Technology Award Finalist in Software Category
Webinar (18)
- Protium FPGA-Based Prototyping Platform
- Augmenting Simulation Via Low-Power Verification Methodologies with Emulation
- Why Debug at Signal Level
- Accelerate Your Verification Debug with the Incisive Debug Analyzer
- Metric-Driven Verification: A Look at How this Methodology Accelerates Verification Process
- Best Practices in Verification Planning
- Tuning Your UVM Environment for Maximum Performance
- Speed Verification Turnaround by Extending MDV to TLM
- What to Do When Code Coverage Closure Seems Impossible
- Optimizing Your Verification Process with Incisive vManager
- UVM SystemVerilog in a Multi-Language SoC World
- Introducing UVM Multi-Language Open Architecture
- Connecting SystemVerilog Real Numbers and Verilog-AMS Nets
- Better Verification Performance with Incisive Enterprise Simulator
- Leveraging SystemVerilog Real Number Modeling
- SimVision Simplifies UVM SystemVerilog Macro Debug
- Simplify UVM Debug with Cadence Incisive SimVision
- Configurable Specman Messaging for Improved Productivity
Success Story Video (6)
- UVM methodology based Verification Environment for Imaging IPs/SoCs
- Plan-Driven Low-Power Verification and Debugging at STMicroelectronics
- NVIDIA Handles Complexity with Palladium Z1 Platform
- Introducing the Palladium Z1 Enterprise Emulation Platform
- AMD - Cadence Palladium XP & In-Circuit Acceleration
- Shorten Verification Time with Specman
Technical Brief (4)
The Palladium Z1 platform uniquely met our requirements due to its reliability as a datacenter compute resource, offering advanced multi-user capabilities and scalability from small four-million-gate verification payloads to multi-billion gate designs.
Daniel Diao, Deputy General Manager of the Turing Processor Business Unit, Huawei
The ability to use the same bring-up flow for Palladium emulation and Protium rapid prototyping allows our design teams to switch seamlessly between the two execution engines, which reduces the prototype bring-up time from months to weeks.
Hideya Sato, Deputy Executive GM, Hitachi, LTD
The Incisive vManager solution has been very well accepted by our design and verification teams because it’s really straightforward, intuitive, and easy to use. The Incisive vManager solution helps us with project visibility, which improves our verification productivity.
Mirella Negro Marcigaglia, Verification Manager, STMicroelectronics
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