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- Two ways for multiple designers to work on the same PCB design
- Shortens the largest portion of your PCB layout design cycle
- Reduces time to route advanced high-speed interfaces by 80%
Globally dispersed PCB design teams are the new reality, which compounds the challenge of shortening design cycle times. Manual workarounds that address multi-user issues are time consuming, slow, and prone to error. The Cadence® Allegro® PCB Designer provides two ways for PCB design teams to collaborate—concurrent team design on a shared canvas and distributed team design with a partitioned canvas. Either way, multiple PCB designers can work on the same design for reduced layout time leading to faster time to market.
Concurrent Team Design on Shared Canvas
The Allegro PCB Symphony Team Design Option expands our existing team design capability by focusing on shortening the largest portion of the PCB layout design cycle. The shared canvas provides a low overhead environment to enable multiple designers to work on the same design at the same time without the set-up requirements of a partitioned project. The more routing engineers you add, the faster your team can finish routing.
By connecting users to a common Allegro database, this simple approach allows multiple PCB designers to easily work on the design at the same time, and any changes made on their canvases are reflected on the server and seen by other users.
It offers two easy-to-use modes. In a normal situation, the design can be hosted in a network server where multiple users can get access to the server and start the concurrent design process. Or, at a moment’s notice, a designer can quickly share their active design in Allegro PCB Editor using the concurrent process on their local machine and invite others users to join the design. In both modes, users can join or leave the session at any time, knowing that all design updates have been updated to the master database.
Allegro PCB Concurrent Team Design technologies support the following Allegro PCB Editor features including TimingVision and interactive etch-editing capabilities, so you can work synchronously together to improve overall productivity and reduce design cycles.
Allegro TimingVision™ technology provides an innovative and unique environment that allows designers to see real-time delay and phase information right on the routing canvas. With the embedded route engine, the Allegro TimingVision environment provides real-time feedback during interactive editing and enhances the designer’s ability to develop a strategy for resolving timing on large buses or interfaces such as DDRx and PCI Express® (PCIe®) Gen3. Coupled with the Allegro auto-interactive phase tune (AiPT) and auto-interactive delay tune (AiDT) capabilities, this environment shortens timing closure of high-speed PCB interfaces by up to 75 percent.
Interactive Etch-Editing Capabilities
Interactive etch-editing capabilities enable real-time, shape-based, any-angle, push/shove routing, which now includes improved arc route handling. It allows designers to view a real-time, graphical heads-up display of how much timing slack remains for an interconnect that has high-speed constraints. Interactive routing also enables diff pair and group routing on multiple nets and interactive tuning of nets with high-speed length or delay constraints. Users can shorten the time to route designs using the Allegro PCB Concurrent Team Design capability using interactive etch-editing commands and AiPT and AiDT capabilities, as well as dynamic shape voiding during routing.
Distributed Team Design on Partitioned Canvas
The second option, the Allegro PCB Design Partitioning Option (also available separately), allows users to work on individual sections of a design exported from a master design. Partitioning a design into multiple sections or areas for layout and editing by several design team members accelerates the time to complete the layout process. Designs can be partitioned vertically (sections) with soft boundaries or horizontally (layers). Thus, each designer can see all partitioned sections and update the design view for monitoring the status and progress of other users’ sections. Such partitioning can dramatically reduce overall design cycles and accelerate the design process.
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