This growing library of informational videos will give you helpful tips on how to use Cadence® Sigrity™ tools to accomplish important signal integrity (SI)- and power integrity (PI)-related tasks. While these videos are meant to explain “how to” for the tool user, they also spend a little time on why each particular task is important in the overall design methodology.
Sigrity Tech Tip: How to Share Power Delivery Network Design Analysis across the PCB Design Team
Learn about the Allegro® Sigrity PI Base and the Allegro Sigrity PI Signoff and Optimization Option from Cadence in this demonstration. Sigrity technologists guide you step by step on how to automatically set-up PDN simulation from schematics, collect and verify components models as early as possible. And make it possible to reshape your design team to make power delivery network (PDN) design and analysis a shared responsibility of the entire team with the latest PowerTree™ technology.
Sigrity Tech Tip: How PCB Designers Can Find and Fix Power Integrity Problems
Learn about Allegro Sigrity PI Base through a demonstration. Sigrity technologists show how PCB designers are empowered to solve basic PI problems early in the design cycle working cooperatively with, but independent from, power integrity engineers. The demonstration will guide you step by step on how to place effective decoupling capacitors, perform DC analysis using the Sigrity PowerDC™ engine, and cross probe with PowerDC report files.
Sigrity Tech Tip: How PCB Designers Can Create Initial PDN Constraints Without Becoming a PI Expert
Sigrity technologists guide you step by step on how to set up your power delivery network (PDN) constraints by using straightforward IPC calculations, instead of waiting for power integrity (PI) experts to establish constraints. Learn about the Allegro Sigrity PI Base and the Allegro Sigrity PI Signoff and Optimization option.
How to Resolve Common IC Package Electrical Concerns
Allegro Package Designer and Sigrity XtractIM™ technology from Cadence are demonstrated. Sigrity technologists guide you step by step on how IC package designers can conveniently identify electrical problems throughout the design cycle. Following this methodology, experts are enabled to focus on the difficult problems without getting overloaded and design cycles times are reduced.
How to Build Accurate Leadframe Package Models Quickly and Easily
Allegro Sigrity SI Base and the Allegro Sigrity Package Assessment and Extraction Option are demonstrated. Sigrity technologists guide you step by step on how to set up a leadframe package design for accurate extraction using the 3D quasi-static solver engine. Accurate RLC extraction is performed on a leadframe design from the same environment used to model multi-layer packages with other solver engines. Design productivity is improved by enabling a common environment to model leadframe, flip-chip, and wirebond IC packages.
How DDR Interfaces Can Be Accurately Analyzed Pain-Free
Learn how to use the Sigrity Finite Difference Time Domain (FDTD) simulator to accurately predict the impact of simultaneous switching noise (SSN) in a system context.
How PCB Designers Can Jump Start Electrical Sign off Using Power-Aware Rule Checks
Sigrity technologists guide you step by step on how to utilize power-aware electric rule checks to confidently fast track the signoff process for your PCB designs.
How to Find Signal Integrity Problems on an Unrouted PCB
Learn about Allegro Sigrity SI Base and the new flow planning feature for route planning with signal integrity analysis through a brief demonstration. Sigrity technologists guide you to discover many signal integrity problems as soon as a PCB design has been placed. The methodology enables finding and fixing many signal integrity concerns without having to rip up and re-route a design.
To receive emails about future Sigrity Tech Tips or other signal and power integrity news, join our email list.