Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview
- Production- and foundry-proven flow with multiple tapeouts
- Direct integration with PDK-driven PVS DRC/verification provides graphical designer feedback minimizing path to tapeout readiness
- Advanced WLCSP-specific metal creation and management removes/reduces eco spins
- High-performance GDSII processing shortens path to tapeout readiness
NOTE: Cadence Physical Verification System (PVS) is mandatory for the WLCSP design flow but must be purchased separately.
The Cadence® SiP Layout WLCSP Option in conjunction with the Cadence Physical Verification System (PVS) delivers flexible advanced wafer-level chip-scale package (WLCSP) design coupled with process development kit/rules deck (PDK)-driven design rule checking (DRC), verification, and mask signoff suitable for emerging silicon wafer-based packaging methodologies, and has been validated by TSMC for their Integrated Fan-Out (InFO) process.
The Cadence SiP Layout WLCSP Option in conjunction with PVS enables designers to address the common advanced (WLCSP) design and fabrication challenges of:
- Adherence to a PDK from the WLCSP manufacturer for DRC, verification, and mask signoff
- PDK-required fan-out wafer-level chip-scale package (FOWLCSP)-specific interconnect (metal) density creation and management to control fabrication warpage
- High-performance GDSII mark processing
- 2D and 3D extraction, model, and analysis for signal and power integrity performance and stability (through optional Cadence Sigrity™ technology)
Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview