IC Package Design and Analysis
The complexity and performance requirements of today’s semiconductor packages continue to increase while design resources remain static for most organizations—placing a premium on efficiency and productivity. Cadence® IC packaging and multi-fabric co-design deliver the automation and accuracy to expedite the design process as part of a comprehensive environment that also includes analysis.
With complex advanced packages, you are faced with power integrity (PI) and signal integrity (SI) issues driven by increasing IC speeds and data transmission rates combined with decreases in power-supply voltages and denser, smaller geometries. Stacked die and packages, higher pin counts, and greater electrical performance constraints are making the physical design of semiconductor packages more complex. To address these issues, you need advanced PI and power-aware SI Sigrity™ tools that can be used throughout the design process.
Die bump planning and optimization is a critical part of our SoC and ASIC design process in order to meet our performance goals. Using OrbitIO helps us achieve our goals in an efficient manner and enabled us to reduce design time by up to 60 percent, while delivering the quality of results our customers expect.
Jim Wang, Senior Associate Vice President, Faraday