Stratus High-Level Synthesis

The first high-level synthesis platform for use across your entire SoC design, Cadence^® Stratus™ High-Level Synthesis (HLS) delivers up to 10X better productivity than traditional RTL design. Based on more than 14 years of production HLS deployment, the Stratus tool lets you quickly design and verify high-quality RTL implementations from abstract SystemC, C, or C++ models. Using the platform, you can reduce the intellectual property (IP) development cycle from months to weeks.

With Stratus HLS, you can easily create abstract models using its integrated design environment (IDE) and synthesize optimized hardware from those models. You can then retarget these models to new technology platforms and reuse them more easily than you could traditional hand-coded RTL. You can actively make tradeoffs between power, area, and performance from within the HLS environment. 

Users have reported productivity as high as 2 million verified gates/designer/year, compared to 200,000 with the traditional RTL flow. For more details, read the Stratus HLS datasheet.