Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview
- Improves full-chip signoff productivity via seamless integration with Cadence Physical Verification System, complete full-chip DRC/LVS/ERC review, job submission, and error analysis within a single cockpit
- Fast loading, editing, and analysis of large layouts for GDSII and OASIS
- Easy-to-use, high-performance standalone chip-finishing system, with support for LEF/DEF format for digital design review
Cadence® QuickView Signoff Data Analysis Environment is the industry’s production-proven full-chip high-performance, high-capacity data-viewing, and standalone chip-finishing system that supports multiple formats of design, layout, and manufacturing data.
The QuickView Signoff Data Analysis Environment is an easy-to-use, high-performance, and standalone chip-finishing system that supports multiple formats of design, layout, and manufacturing data. The QuickView Signoff Data Analysis Environment loads large layouts (GDSII, OASIS, LEF/DEF, and manufacturing formats) in seconds, and provides a rich set of debugging features, including net connectivity tracing, visualization, overlay, and GDSII/OASIS editing.
After full-chip verification, opening the database for chip finishing can take hours, and because there are several iterations at this stage, any productivity loss has a large impact.
Tatsuji Kagatani, Department Manager, Design Automation Department System Integration, Renesas Electronics Corporation