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- Massively parallel architecture that delivers up to 5X faster signoff extraction for all designs
- Fully certified down to 10nm process at TSMC and ready for 7nm designs, as well as all other leading foundries
- Supports better, faster design correlation and convergence, and in-design signoff methodology
- Fastest post-layout simulation and characterization runtimes, ~2.5X better than competitive products
- Comprehensive, accurate and trusted EMIR solution with Cadence Voltus™-Fi Custom Power Integrity Solution for all FinFET designs
Cadence® Quantus™ QRC Extraction Solution is the industry’s most trusted signoff parasitic extraction tool. It’s an integral component of our in-design methodology with both Innovus™ Implementation System and Virtuoso® platforms. Quantus QRC Extraction Solution is built on massively parallel technology and includes an integrated, foundry-certified field solver (Quantus FS). As a result the solution delivers up to 5X faster signoff extraction and silicon-proven accuracy for system-on-chip (SoC), custom-digital, standard-cell, IP, SRAM/bitcell, memory-IC, and custom-analog designs. As a single, unified tool, Quantus QRC Extraction Solution supports both cell-level and transistor-level extractions during design implementation and signoff.
As advanced process geometries continue to shrink, parasitic extraction becomes a necessity throughout the design implementation flow and the validation phase. Quantus QRC Extraction Solution supports all designs down to 10nm and early 7nm design starts. For FinFET designs new modeling challenges emerge. For example, the introduction of FinFET 3D device structures bring more complex parameters for parasitic capacitance and resistance. These new challenges require the highest level of accuracy in signoff extraction. Quantus QRC Extraction Solution addresses these challenges with its robust modeling infrastructure, which delivers the highest accuracy models and produces the smallest netlist to enable faster simulation and characterization runtimes.
After validating the runtimes of Cadence’s Quantus QRC Extraction Solution on benchmark designs, we have determined that it offers significant improvements without compromising signoff accuracy.
Sumbal Rafiq, Director of Engineering, AppliedMicro
Despite increasing SoC design sizes and interconnect process corners at advanced nodes, Open-Silicon has achieved design closure quickly by using the Quantus QRC Extraction Solution along with its best-in-class design methodologies and tools.
Radhakrishnan Pasirajan, Vice President of Silicon Engineering, Open-Silicon
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