Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview
- Improves systematic and parametric yield
- Meets DFM foundry requirements
- Integrates with Cadence custom and digital design platforms
- In-design and signoff model-based litho checks with the LPA PLUS
Cadence® Litho Physical Analyzer detects and corrects lithography hotspots, and does so quickly, based on either fast, accurate silicon contour prediction, or high-performance pattern matching.
Litho Physical Analyzer detects manufacturability issues missed by traditional physical verification. Depending on the foundry enablement, the tool can either perform a pattern-based check or use a simulation engine to meet foundry litho requirements. Litho Physical Analyzer not only provides foundry-certified fast-litho detection for signoff, it also allows hotspots to be detected during implementation through tight integration with custom and digital implementation platforms. The solution provides fixing guidelines to increase automated fixing rates.
In addition to litho checks, Litho Physical Analyzer can perform pattern-based layout optimization to improve design quality, increase usage of DFM rules, and automate the fixing of complex design rules.
- Provides fast, scalable and foundry-certified detection of yield-limiting hotspots to meet litho signoff requirements
- Produces fixing guidelines to increase automated fixing rates
- Integrates with current library, IP, custom analog, and cell-based digital physical design flows
- Delivers versatile pattern-based layout optimization to improve design quality
At advanced nodes, definition of design rules and process options must be tightly optimized to deliver the best tradeoff for performance, power, area, and manufacturability. However, implementation platforms don’t typically have access to process information and process teams don’t have design knowledge, both of which hinder a customer’s ability for design-technology-co-optimization (DTCO).
With an integrated Tachyon OPC engine, the Cadence Litho Physical Analyzer Production Lithography Unified Solution (LPA PLUS) performs lithography checks using the foundry process recipes and leverages the LPA integration for both custom and digital design platforms. It is also capable of handling signoff as a standalone. As a result, designers can improve design reliability and yield, while also accelerating time to market and yield ramp-up of their products.
To meet our time-to-market goals, DFM solutions at 28nm need to deliver low cost of ownership, accurate silicon predictability, and high performance.
S.C. Chien, Vice President of IP and Design Support Division, UMC
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