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- Accurately predicts multi-layer thickness and topography variability for the entire layer stack using a model-based approach developed with model calibration tool, Cadence CMP Process Optimizer
- Detect hotspots that affect yield and produces fixing guidelines during implementation through integration with Cadence Virtuoso Layout Suite and Cadence Innovus Implementation System at chip or block level
- Interfaces with Cadence Quantus QRC Extraction Solution to identify timing-related problems and potentially reduce process guardbands
- Enables CMP teams to detect CMP hotspots on incoming designs, optimize the CMP manufacturing parameters, and improve overall systematic and parametric variations
Cadence® CMP Predictor predicts the Chemical and Mechanical Polishing (CMP) variations and their potential impact on your design for the entire layer stack. It turns the uncertainty of manufacturing process variation into predictable impacts, and then minimizes these impacts during the design stage to greatly enhance overall design performance and yield, at the chip level and also at IP level with CCP unique block-based methodology. CMP predictor allows silicon calibration of semi-physical models and optimization of CMP material and process parameters. CMP Predictor provides full-chip, multi-level thickness and topography predictions for the entire stack, covering FEOL, MEOL, BEOL, dielectric deposition, copper electrochemical deposition (ECD), etch depth, and copper/dielectric planarization processes.
CMP-related hotspots, such as copper pooling, can have detrimental effects on chip yield. The conventional rules-based approach to hotspot detection fails to capture long-range and multi-level CMP effects. CMP Predictor uses a highly accurate model-based approach to finding potential hotspot areas. It also feeds the thickness and topography variation data into extraction tools, enabling better RC and timing analysis.
Cadence CMP Predictor integrates with Cadence Virtuoso® Layout Suite, Cadence Innovus™ Implementation System and interfaces closely with the Cadence Quantus™ QRC Extraction Solution for a complete silicon signoff solution.
The Cadence massively parallel architecture allowed us to significantly reduce the time spent in signoff analysis, implementation, and closure so we could quickly deliver a quality reference design to market.
Shih Chin Lin, Senior Division Director, IP Development and Design Support Division, UMC
Working together with Cadence, we’re driving advances in CMP process performance.
Derek Witty, Vice President and General Manager, CMP Products Group, Applied Materials
After an extensive evaluation of all vendors in the market, we selected the complete Cadence DFM set of technologies for our most advanced ASIC and SoC designs.
Hiroshi Ikeda, Director of the System LSI Technology and Design Platform Development Department, Fujitsu Semiconductor Limited
Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview