Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview
- The industry’s first static timer integration for constraints and CDC signoff enables modeling the design and constraints, using the same interpretation as the Tempus Timing Signoff Solution, to provide customers with 100% signoff accuracy at the RTL
- CDC signoff verifies structural correctness of CDC in the design from early RTL through implementation
- Constraints signoff checks for correctness and completeness of constraints at the IP level and lets users perform hierarchical block versus top consistency checks at the SoC integration level
- Smart analysis generates accurate low-noise reports, providing insights into the design and the constraints intent and enabling users to diagnose root cause failures and signoff rapidly, thereby saving weeks to months in the design schedule
- Multi-CPU parallelization delivers up to 10X faster turnaround time on SoC designs
SoCs are built hierarchically by assembling subsystems. The subsystems are comprised of legacy designs and many commercially available IP. The IP and their respective timing constraints are developed and validated with their own timing-intent goals before the subsystems and SoCs are realized. Verifying correctness and completeness of the constraints at the IP level and consistency at the SoC level is critical for converging on signoff-quality constraints.
To address these requirements of constraint signoff, Conformal Litmus offers a rich set of built-in rules to verify issues such as missing constraints, timing exception overlaps, and conflicts at the IP level. It also verifies that the intent of the IP-level constraints is consistent with that of the SoC-level constraints.
The Conformal Litmus smart analysis generates accurate, low-noise reports that shorten debug time and help users achieve signoff-quality constraints rapidly.
Timing constraints are transformed and undergo several refinements as the design progresses from RTL to final layout. During this journey, the design and timing constraints change and may lose the original intent.
For example, synthesis optimizations like cloning, decloning, and buffering could unintentionally corrupt the original intent of the constraints. ECOs can introduce logic that can be erroneously affected by a timing exception.
Logic equivalency checking can ensure that the design intent is equivalent before and after an implementation step. But the designer will also need to verify that the timing constraint intent is also equivalent. If these constraint equivalence checks are not performed, this could result in schedule delays or potentially costly re-spins.
Conformal Litmus offers constraints comparison capabilities, wherein the user can make sure the timing constraints from a previous step in the implementation flow are in sync with the current step. These checks are needed to make sure the constraints intent is preserved from one step to the next, all the way to tapeout.
SoC systems have multiple interfaces and sub-blocks that operate on clock domains inherently asynchronous to each other. The designs have extremely complex asynchronous clock schemes that must be verified at every stage in the design flow. If unverified, these crossings can be catastrophic and cause costly chip re-spins.
The Conformal Litmus CDC signoff verifies correctness of CDC structures between the asynchronous clock domains from early RTL through implementation flows.
- Easy setup: Supports timing signoff constraints and includes a TCL scripting environment with powerful control and reporting capabilities. It also supports the Cadence Stylus Common User Interface
- Comprehensive CDC verification: Conformal Litmus performs comprehensive checks to verify proper implementation of synchronization schemes to mitigate metastability and to prevent glitches and re-convergence. Conformal Litmus also verifies the correctness of complex CDC structures, including handshake synchronizers, bus synchronizers, and FIFOs
- Smart signoff: After performing comprehensive analysis, Conformal Litmus presents the results in a very intuitive way. All insights required to understand the CDC intent are readily available, which helps users to diagnose root cause failures easily and signoff rapidly
- Capacity: The Conformal Litmus multi-CPU parallelization infrastructure can process very large SoC-level designs and is scalable to billion gate design sizes.
- Gate-level netlist verification: Post-synthesis, various insertion steps (such as power, test, scan etc.) can introduce unintended crossings. The Conformal Litmus gate-level netlist analysis can identify these erroneous domain crossing paths that can be potentially catastrophic for the chip
Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview