Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview
- Foundry-golden, comprehensive, model-based litho hotspot analysis
- Industry’s first in-design, constraint-driven layout-dependent-effects variability detection and optimization
- Higher productivity and more predictable tapeout schedules
Cadence® Virtuoso® DFM enables designers to accurately assess both physical and electrical variability to ensure the manufacturability of custom and mixed-signal designs, libraries, and IP—without ever leaving the Virtuoso Layout Suite environment.
Virtuoso DFM preserves design intent (such as electrical constraints), ensures fast convergence on design goals through accurate abstraction, and provides highly convergent results through near-linear scalability and automatic fixing of errors. This enables engineers to implement a “correct-by-design” flow, so they can efficiently and predictably reach tapeout on leading-edge designs with multiple foundry partners.
Virtuoso DFM allows designers to identify, analyze, and automatically optimize the design’s on-chip parameters for the impact of physical effects such as lithography, mask, OPC, etch, and RET; as well as layout-dependent effects such as litho, overlay, context-dependent stress, strain, well proximity, unintentional stressors like shallow-trench isolation, contact-to-contact spacing, and more. In addition, the Virtuoso in-design methodology provides an accurate, model-based flow for designers to minimize the impact of manufacturing variations on design performance.
- Minimizes design iterations with slack-driven engine
- Handles large designs through massively parallel architecture
- Improves cross-corner variability
- In-design DFM and predictable DFM closure for custom design implementation
- Production-proven “golden” pattern matcher for in-design DRC+ for GLOBALFOUNDRIES 28nm process