Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview
- Shared engines across design and characterization ensure consistency of results
- Better overall throughput through tight integration between different tools
- One-stop shop for all memory design, verification, and characterization needs
On today’s SoC designs, the memory and memory arrays take up a lot of real estate and are often in the critical path for timing, yield, and schedule. Due to ever-increasing memory size demand, design and verification engineers are faced with multiple challenges, such as time to market due to an aggressive schedule, the use of different point tools such as SPICE and FastSPICE simulators, characterization utility, and the consistency that is required across the tools.
The Cadence® Legato™ Memory Solution is the industry’s first integrated solution for memory design, verification, and characterization. Eliminating the complexity of piecing together point tools for multiple design and verification tasks, Legato Memory Solution provides one platform for all memory design, verification, and characterization needs, maximizing the simulation throughput and leading to a 2X runtime improvement while maintaining the accuracy.
The new solution is built on the golden-, industry- and silicon-proven simulation and characterization engines of Cadence Spectre® and Liberate® and includes a new patent-pending Super Sweep technology that utilizes existing simulation databases for multi-corner and Monte Carlo analysis, allowing designers to improve both runtime and simulation throughput.
The Cadence Legato Memory Solution consists of three environment cockpits: cell design, array and complier verification, and memory characterization. With the cell design cockpit, engineers can design the bitcell and get Monte Carlo variation analysis. When accessing the array and compiler verification cockpit, design and verification of full memory arrays occurs while accessing new tools, like Super Sweep, to maximize accuracy and simulation throughput for advanced-node designs. Finally, in the memory characterization cockpit, a Liberty library format of the memory is created and can used for SoC full-chip analysis.
This one-of-a-kind solution gives engineers a cohesive design environment that automates design steps, ensures consistency, and allows designers to use the Cadence toolset to deliver products to market faster. With the Cadence Legato Memory Solution, designers can improve productivity while meeting demanding design schedules. View our Legato Memory Solution videos for more details on the solution.
Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview