Cadence® custom simulation technology delivers all the tools required for designing and verifying your analog/ mixed-signal blocks. Cadence offers multi-core, distributed SPICE simulation for realizing your design intent; higher capacity, performance, and throughput with a new and advanced FastSPICE algorithm, using the same infrastructure and use model; and a mixed-signal simulation solution that leverages logic verification methodologies to improve your overall verification methodology. Cadence also delivers capabilities to abstract your design for architectural exploration and top-down verification methodology support.
Leveraging custom design abstraction capabilities, Cadence chip-level simulation looks at all the blocks abstracted into a variety of languages combined with transistor-level blocks that converge on a whole design understanding. Cadence chip-level simulation solutions provide the large capacity and high performance required to ensure that a full chip is working as intended, regardless of how the blocks perform in aggregate.
Today’s system-on-chip (SoC) designs integrate complex analog and digital blocks, requiring thorough testing and analysis of how analog and digital circuits interact and the influence they have on each other. Cadence mixed-signal simulation solutions blend output results from industry-leading block-level and full-chip analog simulators with output from advanced digital analysis technologies. This superior approach to analysis also includes an extensive multi-language capability to support design abstraction and the ability to add in RF information.
With our Spectre® platform, you have tools with a common infrastructure, advanced simulation database, versatile front-end parser, and a robust device library. Through integration with our Virtuoso®, Allegro®, and Innovus ® solutions, the Spectre tools deliver comprehensive design and verification.