Circuit Simulation

Block-Level Simulation

Cadence^® custom simulation technology delivers all the tools required for designing and verifying your analog/mixed-signal blocks. Simulating blocks has evolved since the days of op-amps and comparators. Consider a typical block such as a fractional-N PLL that has more devices than some traditional analog chips. For block-level design, the steady-state analysis provided by the Spectre^® platform can be invaluable for evaluating the noise and transfer functions of blocks like dynamic comparators, time-to-digital converters, et cetera. Block-level verification includes long transient simulations to calibrate blocks, for example, VCO calibration. For blocks, transistor-level simulation is used for verification and it may require transient noise analysis to simulate the key parameters like phase noise. 

Chip-Level Simulation

Leveraging custom design abstraction capabilities, Cadence chip-level simulation looks at all the blocks abstracted into a variety of languages combined with transistor-level blocks that converge on a whole design understanding. Cadence chip-level simulation solutions provide the large capacity and high performance required to ensure that a full chip is working as intended, regardless of how the blocks perform in aggregate.

Mixed-Signal Simulation

Today’s system-on-chip (SoC) designs integrate complex analog and digital blocks, requiring thorough testing and analysis of how analog and digital circuits interact and the influence they have on each other. Cadence mixed-signal simulation solution combines the industry-leading digital and analog circuit simulators: Xcelium^® and Spectre, to provide designers and verification engineers superior performance and accuracy required for today’s designs.

With the Spectre platform, you have tools with a common infrastructure, advanced simulation database, versatile front-end parser, and a robust device library. Through integration with our Virtuoso^®, Allegro^®, and Innovus^® solutions, the Spectre tools deliver comprehensive design and verification.