Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview
- Speeds common design entry tasks by 5X
- Eases the development of multiple tests over multiple conditions to validate a design’s performance against the target specification
- Allows advanced user to quickly execute commands using user-programmable bind keys and object-sensitive pop-up menus, which display relevant operations
- Enables adding design constraints to the schematic to maintain consistency and preserve the designer's intent on critical pieces of the design (XL)
- Speed simulation by using schematic blocks to ceate Verilog wreal models
- Easily develop low-power models for analog and custom digital components through a simplifier user interface (in the Cadence Power Format or CPF)
The Cadence® Virtuoso® Schematic Editor provides numerous capabilities to facilitate fast and easy design entry, including design assistants that speed common tasks by as much as 5X. Well-defined component libraries allow faster design at both the gate and transistor levels. Sophisticated wire-routing capabilities further assist in connecting devices. For larger and more complex designs, the Virtuoso Schematic Editor not only supports multi-sheet designs but also provides the ability to design hierarchically, with no limit on the number of levels used. The Hierarchy Editor makes hierarchical designs easy to traverse, and automatically ensures all connections are maintained accurately throughout the design.