- Ability for digital designers to “push into” analog blocks and view their layouts
- Robust mixed-signal router that can understand analog constraints such as symmetry and differential pair routing
- Automated timing-, congestion-, and power-aware floorplanning and pin optimization
- Advanced low-power support
- Full-chip timing and signal integrity signoff extending to digital content in AMS blocks
Today's applications are driving the need for higher levels of analog/mixed-signal (AMS) content on systems on chip (SoCs). As AMS circuits grow larger and more complex, so have the SoC implementation challenges. Addressing the growing number of interfaces and functional interactions between the analog and digital circuits requires a new and more innovative approach to mixed-signal implementation rather than the traditional practice of importing hardened AMS IP.
Using the Digital-on-Top (DoT) methodology, the final layouts for the completed AMS IP are loaded into the Cadence® Innovus™ Implementation System, a single environment that supports RTL synthesis, full-chip silicon virtual prototyping, floorplanning, placement, routing, block implementation, full-chip integration, and in-design signoff and chip finishing. In addition, the system supports the implementation of high-performance, low-power, Giga-scale mixed-signal designs and meets the manufacturing requirements of 28/20nm advanced-node designs.
Using OpenAccess as a single design database, analog and digital designers retain their own preferred design environments while increasing implementation efficiency with seamless data sharing between the Cadence Virtuoso® platform and full-flow digital design solution. Both the analog and digital teams can easily see the complete design and any changes implemented by their peers. The interoperability between design environments has proven extremely valuable during the late design stages when both analog and digital design teams need to carefully coordinate and agree on potential modifications. A single design database allows everyone on the team to see the current design, and its status, in their own environments. Engineering change orders (ECOs) are much more efficient since they no longer require the generation of LEF/DEF/GDSII files to communicate the changes.