Machine and deep learning algorithms present the opportunity to transform the electronics industry and create a new silicon renaissance with advances in software and IP. The electronics industry is addressing larger and larger volumes of design and simulation data that increase complexity and challenge productivity.
Cadence has been using machine learning in our products since 2013 and continues to push the leading edge to improve usability and performance. Machine and deep learning can be used for internal and external use models that serve different needs. Internal improvements include increased performance and accuracy for existing tools and technologies. External improvements include modifications to existing design flows and methodologies to improve productivity.
Automation has been a fundamental driver of EDA technology from the start, and the push to improve designer productivity never slows as the complexity of chip designs increases. Cadence has already established a leadership role in software and IP, having implemented machine learning in current products to improve productivity and performance and ultimately, more automation through intent-driven design.
To meet the needs of our customers, Cadence continues to employ the latest in machine learning techniques throughout the company in two major areas:
- Improving our tools and flows. We have a major company-wide initiative to utilize machine learning techniques throughout our design tools to make our tools easier to use and improve the designer experience.
- Improving our IP. Much of our IP is used in machine learning applications, from our customizable Tensilica® processors to the standard interfaces to memories and I/Os.
Cadence is active in machine and deep learning research including research in adjacent technologies such as data analytics, optimization and distributed computing architectures. Cadence is a member of the Center of Advanced Electronics Through Machine Learning (CAEML), working with research universities to accelerate advances in design, simulation and verification methods for EDA.
Cadence Selected for Machine Learning Contract by DARPA
In July 2018, Cadence announced that it has been selected by the Defense Advanced Research Projects Agency (DARPA) to support the Intelligent Design of Electronic Assets (IDEA) program, one of six new programs within DARPA’s Electronics Resurgence Initiative (ERI) to use advanced machine learning techniques to develop a unified platform for a fully integrated, intelligent design flow for systems on chip (SoCs), systems in package (SiPs), and printed circuit boards (PCBs). The ERI investments are the next steps in creating a more automated electronics design capability that will benefit the aerospace/defense ecosystem and the electronic industry’s commercial needs. See press release.
To fulfill the program charter over the four-year term of the contract, Cadence created the machine learning-driven Automatic Generation of Electronic Systems Through Intelligent Collaboration (MAGESTIC) research and development program. This program will create a foundation for system design enablement by introducing greater autonomy within the design process and developing truly design-intent-driven products. The Cadence-led team includes Carnegie Mellon University and NVIDIA, two of the most renowned machine learning leaders in the world.
The DARPA ERI programs address impending engineering and economics challenges that, if left unanswered, could challenge what has been a relentless half-century run of progress in microelectronics technology. It is now clear that the design work and fabrication required to keep pace in microelectronics is becoming increasingly difficult and expensive. The MAGESTIC program aims to address:
- Advancing the state of the art in machine learning to develop algorithms that optimize performance
- Extending support for advanced CMOS process nodes including 7nm and below, as well as larger process nodes
- Automating the routing and tuning of devices to improve reliability, circuit performance, and resilience
- Demonstrating improved power, performance, and area (PPA) utilizing machine learning, analytics, and optimization
- Staging the introductions of the technology, allowing the system to learn from the users and allowing users to gain an understanding of how to best leverage the tools to achieve desired results
The program will extend Cadence’s work in employing cloud-based design systems to handle large-scale distributed processing to speed design efforts.
Improving Our Tools and Flows
We’re already using machine learning techniques to produce better, more predictable outcomes for many tasks in the EDA flow. But there are so many more potential areas for improvements. Machine learning can help our customers meet their product time-to-market requirements if we can make the design process smarter and reduce the amount of manual intervention necessary. The goal is to allow our tools to suggest solutions to common problems that might otherwise take design teams weeks or months to evaluate.
Cadence is using combinations of statistical models with increasing sophistication in our simulation, verification, analog, power analysis, place-and-route, and modeling tools. Our first “modern” machine learning-enabled tools were Virtuoso Electrically Aware Design and Analog Design Environment in 2013. The Electrically Aware Design Environment uses analytics and machine learning technologies for rapid in-design parasitic extraction. The Analog Design Environment uses machine learning for mismatch modeling for design tuning and verification. Machine learning models are also used in our Stratus High-Level Synthesis tool to create models that speed designer productivity over traditional RTL design.
Advances in massively parallel computing architectures are opening the door for “what if”-based optimization and verification to explore the design space efficiently and converge on the most promising designs that still meet intent.
For advanced-node designs, there is an increase in uncertainty presented by new silicon technology and additional verification needs. Cadence is employing machine learning techniques to its Liberate family of products to speed library characterization, using it for memory or logic gate power estimation or timing.
While there’s a lot Cadence can do to employ machine learning in our tools, there’s even more we can do to help our customers employ machine learning in their designs, as that’s where a lot of the relevant data is generated. We are also pushing the leading edge of machine and deep learning research to improve the design of digital ICs and verification closure with a vision toward design improvement. The Cadence machine learning team leverages our libraries of algorithms across platforms and products to ensure each wave of innovation impacts the breadth of our EDA and IP solutions.
Our IP Enables Machine Learning
So many of our customers are designing applications that involve machine learning that we have examined our IP portfolio to make sure we have the right processors and interfaces to make their designs successful.
Running computationally complex algorithms on standard processors often does not give the performance or power efficiency necessary for the compute- and data-intensive machine learning/AI applications. Cadence has two answers for this dilemma:
We were the first company to introduce controller and PHY IP for the Cache Coherent Interconnect for Accelerators (CCIX), which enables machine learning. The CCIX interface addresses a major challenge—quickly handling all the data required for machine learning algorithms. The CCIX interconnect provides memory coherency among multiple processors and accelerators, and eliminates much of the latency problem with conventional architectures. Find out more about CCIX from this Semiconductor Engineering article.
We have specifically optimized our Tensilica processors for on-device AI processing. Check out our Vision DSPs for vision and neural network processing. These are particularly good at AI-inferencing applications, including classification, segmentation and object detection, for vision, radar/lidar and communication products. Cadence provides a comprehensive AI software platform including the Tensilica Xtensa® Neural Network compiler (XNNC) for mapping neural networks into highly optimized high-performance code for the targeted DSP.
We also have optimized Tensilica processors for speech recognition. See our HiFi DSPs.
Most machine learning applications are designed for leading-edge process nodes, as that’s where the highest performance can be achieved. The entire Cadence IP portfolio of memory, interface, and peripheral IP is optimized for the latest process technologies. These are essential building blocks in machine learning designs.
For more information, check out our IP website.