- Comprehensive solution for low-power implementation and signoff
- Support for both industry-standard power intent formats (CPF and IEEE 1801), enabling you to adopt the design flow of your choice
- Production proven on 1000s of design,s mitigating risk of re-spins and reducing product development time and costs
The Cadence® low-power solution comprehensively supports design implementation and signoff throughout the flow. If you're using a high-level synthesis (HLS) methodology, you'll benefit from the power-aware architectural/micro-architectural choices that are made available from a very high-level description of the design. This enables making the right trade-offs for power, performance, and area (PPA) at the earliest stages of the design, when it matters the most. Once the RTL and power intent are available for analysis, the Cadence solution helps perform a sanity check of the power intent itself. This prevents unexpected negative surprises as you progress through the low-power flow. The Cadence solution supports both the IEEE 1801 and CPF industry-standard formats for power intent. All aspects of implementation consider the power intent and make trade-offs and optimizations for leakage and dynamic power to deliver a low-power design without unnecessary compromises and with high Quality of Results (QoR). At every stage of implementation, the Cadence solution helps verify that the low-power design is compliant with the specified power intent. Signoff tools are power intent-driven as well, which ensures that the power intent has been implemented correctly to avoid re-spins, eliminate product delays, and reduce product costs. What's more, the Cadence low-power solution has been used in production in 1000s of designs.