The automobile has always been a harsh environment for electronic design and signal fidelity. Now, ever more complex electronic control, rising data rates, and a simultaneous drive for fewer electronic control units (ECUs) per car means significant design, integration, and verification challenges for modern ECUs. Cadence offers design tools across all the PCB, system-in-package (SiP), and SoC fabrics, enabling coherent and integrated ECU design and analysis. See how you can use Cadence® technologies to optimize ECU design.
ECU Mixed-Signal SoC
Cadence has worked closely with all the leading automotive semiconductor suppliers for over a decade, and today, the collaboration continues to refine and improve our industry-leading Mixed-Signal Solution for automotive SoC design. Benefiting from the on-going evolution of the underlying Virtuoso®, Innovus™, Spectre®, and Incisive® platforms, the Cadence Mixed-Signal Solution provides unique and powerful integration of analog and digital platforms, for real-world mixed-signal SoC design. Learn more
Automotive SoCs must demonstrate functional safety, including resilience to failure and fail-safe modes, but they must also provide reliability across their lifetime of operation. For this, Cadence also works very closely with silicon foundries, so aging effects such as hot carrier injection, bias temperature instability, time-dependent dielectric breakdown, electro-migration, and high automotive temperatures (which accelerate aging) are all accounted for in our Mixed-Signal Solution. You can then design reliability into your automotive SoCs.
As the automotive supply chain works towards reducing ECU count and network costs, there is a need for even greater levels of ECU integration, particularly through SiP and SoC fabrics. For many, this can mean adoption of advanced SoC process nodes, which bring a new set of concerns for the automotive SoC designer. Our Cadence Mixed-Signal Solution enables automotive designers to account for advanced-node issues such as layout-dependent effects, FinFETs, local interconnect, multi-patterning lithography, and increased device variation and mismatch. Learn more
- Automotive mixed-signal SoC design can be centered and optimized for reliability, performance, power, area, and thermal profiles
- Automotive mixed-signal SoC verification can be configured across a range of supported languages, abstractions, methodologies, and Cadence simulation engines, and optimally re-configured as SoC block design progresses to integration
- Provides metric-driven, coverage-based mixed-signal SoC verification and traceability for the IS0 26262 standard
- Delivers OpenAccess-based analog and digital implementation, exchange, and signoff
ECUs for advanced driver assistance systems (ADAS) often need multiple sensors to act as the eyes and ears of the car. The integration of these sensors with local compute for sensor fusion is a similar challenge to the integration of multiple inertial sensor die for the smartphone market. Here, SiPs provide a solution that minimizes space, weight, power, and volume costs. The small form factors and profiles of SiP solutions enable OEMs to more discreetly integrate smart sensors into the exterior surfaces of the car.
These same benefits can be achieved with any automotive ECU. The bill of materials (BoM), size, weight, and power of the ECU can all be reduced by integrating multiple bare die and passives directly into the SiP.
Cadence SiP Layout XL is the physical design solution for advanced SiP packages, covering side-by-side die, stacked die, and combinations of the two. It supports design across a wide range of single- and multi-die packaging technologies, including laminate build-up substrates, interposers, and wafer-level fan-out packages. Its 3D-aware design and 3D visualization combines with comprehensive DFM/DFA checking to ensure accurate and efficient implementation of ECU modules and other automotive packaging applications. Learn More
- Comprehensive 3D checking and visualization for error-free, complex, multi-tier wirebond, flipchip, and through-silicon-via configurations
- Constraint-driven layout with auto-interactive routing technologies for fast, accurate implementation of high-density SIP interconnects
- Design tool compatibility with OSAT providers for seamless bi-directional exchange of design data
Automotive ECUs further benefit from size and weight reduction when PCBs designed with Cadence Allegro® tools are miniaturized with fineline multi-layer substrates, blind and buried vias, microvias, substrate embedded passive and active components, and rigid-flex substrates that can be folded and fitted into automotive housings that target specific voids and spaces within the car. Tight Allegro integration with mechanical CAD (MCAD) tools ensures productive ECU co-design of housings and PCBs. Learn more
- Constraint-driven floorplanning, placement and routing, incorporating auto-assisted track-length variation for timing and phase tuning
- Mechanical housing collision detection with 3D visualization of components, shields, and rigid-flex boards
- Cadence PSpice® Advanced Analysis Option, which prevents board failures by determining which components are over-stressed using Smoke analysis or by observing component yields using Monte Carlo analysis
ECU RF for V2V / V2X
Integrated RF design for vehicle-to-vehicle / vehicle-to-infrastructure (V2V/V2X) ECUs can be achieved in PCB, SiP, and SoC fabrics using RF variants of Cadence design tools, with system verification achieved through Allegro Sigrity™ extraction and with Spectre RF simulation. Learn more
- Allegro tools for PCB antenna design and other RF copper shape editing, placement, and routing, including a library of more than 200 RF symbols
- Cadence SiP Layout XL for embedding inductors / passives in the SiP substrate
- Cadence Virtuoso tools for closely coupled RF circuit design and RF layout for SoCs, incorporating parasitic sensitivity analysis and design centering
- Spectre RF for RF system simulation, utilizing SoC/SiP inductor and packaging s-parameter models extracted with Allegro Sigrity tools
ECU Signal, Power, and Thermal Integrity
Automotive ECUs created with PCB, SiP, and SoC fabrics must accommodate harsh thermal and electromagnetic operating conditions within a car. With inter- and intra-ECU data rates also rising dramatically, this demands careful signal, power, and thermal integrity analysis. Gigahertz communications between memory and CPU in SiP and PCB designs within an ECU, or network communication between ECUs, all benefit from signal integrity (SI) analysis with the Allegro Sigrity SI tool, where signal, power, and ground can be coupled and simulated together. And full wave extraction of SiP package, PCB, and connector physical contexts with Cadence Sigrity PowerSI® 3DEM allows detailed analysis of the losses, reflections, ringing, and crosstalk that can impact eye openings in these high-speed ECU communication pathways. Thermal analysis of PCBs and SiPs within the ECU can be achieved with the Cadence Sigrity PowerDC™ tool, which identifies areas of excess current density and thermal hotspots to reduce risk of field failure. Near-field emissions from ECU boards are also available from Sigrity power-aware SI analysis, as part of electro-magnetic compliance (EMC) testing. Learn More
- Sigrity solutions target complete power-delivery system analyses across chips, packages, and boards within an ECU
- Sigrity solutions target SI analysis for ECUs, including simultaneous switching noise (SSN) analysis of high-speed signal transmissions
- Take advantage of constraint-driven design methodology, which ensures electrical design intent is followed and performance verified with power-aware SI analysis technology