- Lower risk to develop ARM® core-based SoCs
- Easy to use for higher productivity
- Shorter timeframe needed to meet PPA targets
- PPA push technology and expertise to help with last-mile closure
ARM typically works with EDA vendors to develop generic EDA reference flows. However, working closely with ARM, Cadence has optimized our full-flow digital solution for ARM-based designs. Using the resulting digital implementation reference flows, you can efficiently implement your ARM core-based systems on chip (SoCs) and reach your power, performance, and area (PPA) targets much faster versus using generic EDA reference flows.
ARM utilizes Cadence® tools to develop its IP. As a result, we have early access to ARM cores, so we can tune our tool algorithms, features, and options, and can optimize our flow before the official release of the ARM cores. Hundreds of floorplan trials, recipe-tuning instances, and flow changes go into a Cadence reference flow for ARM designs. All of this leads to an added PPA and turnaround time (TAT) boost on top of the generic EDA reference flow results.
Flows are available for ARM Cortex®-A, Cortex-R, and Cortex-M cores, multimedia products (GPUs, display controllers, video controllers), and interconnect cores. You’ll get an optimized starting point of scripts, floorplans, and documentation for these CPU and GPU configurations as well as for popular foundry process technologies, including FinFET and other advanced nodes.
Fast Turnaround with Predictable PPA
As you implement the ARM cores on Cadence’s RTL-to-signoff flow, we bring in experienced R&D staff and product engineers who have worked closely with ARM to build reference flows. These technical experts also have experience helping with the PPA push on several tapeouts worldwide on advanced ARM designs, spanning a range of technologies from 40nm to 10nm and below.
Cadence’s digital implementation reference flows are supported by our early collaboration with ARM. With our reference flows, you get design techniques, from RTL to GDSII, for ARM processors, reducing time to silicon with predictable PPA results. Contact your Cadence Sales representative for more information. The flows are also optimized with ARM POP™ IP core-hardening acceleration technology. Using these flows, you’ll be equipped to efficiently produce optimized SoCs based on ARM big.LITTLE™ processing systems.
Optimizing for Low Power
Cadence provides a comprehensive solution to design, verify, and optimize power consumption on ARM-based SoCs:
- Functional verification of all the power modes of ARM cores is accelerated using the Incisive® Enterprise Simulator and Palladium® Z1 emulation platform
- Joules™ RTL Power Solution helps to accurately estimate power at an early stage of the design and to identify peak power under realistic system usage scenarios
- The Genus™ Synthesis Solution and the Innovus™ Implementation System help to concurrently optimize leakage and dynamic power while simultaneously maximizing performance and minimizing area
- Conformal® Low Power is the industry-leading low-power formal tool that is routinely used to validate ARM-based SoC designs
- Cadence signoff tools, including Tempus™ Timing Signoff Solution, Quantus™ QRC Extraction Solution, and Voltus™ IC Power Integrity Solution, help accelerate signoff, so you can tape out ARM-based SoCs with confidence
- All tools in the low-power flow support power intent for ARM-based SoCs described in industry-standard CPF and IEEE 1801 power formats
We partnered closely with Cadence to utilize the Innovus Implementation System during the development of our ARM Cortex-A72 processor. This demonstrated a 5X runtime improvement over previous projects and will deliver more than 2.6GHz performance within our area target.
Noel Hurley, General Manager, CPU Group, ARM