- Allows heterogeneous integration of different dies
- Improves performance
- Reduces power consumption
- Provides maximum functionality in a smaller form factor to support numerous applications in networking, graphics, mobile communications and networking
Ever wonder when the law of physics will come into play with semiconductor designs? Thankfully, plenty of scientists and engineers are working hard to extend the laws as we have known them for IC and SoC design. 3D-IC technology is an alternative path (often called “more than Moore’s”) to further extend Moore’s Law in order to generate higher bandwidth, lower power consumption, and reduced area without traditional process scaling. The technology applies to various applications, from networking and high-performance computing to wearables and the Internet of Things (IoT).
As with any new solution, 3D-IC comes with unique new challenges, including:
- Thermal management: The through-silicon-vias (TSVs) in 3D-ICs can result in poor lateral heat distribution, more heat dissipation, and reduced performance if not managed properly
- Test strategies: Test access is only at the bottom die, so you’ll need a design-for-test methodology that propagates test stimuli and responses up and down through the stack to better identify problem points
- Other design enablement: Electronic design automation (EDA) requires some enhancement for 3D-ICs, from package silicon co-design to new layout layers, new extraction features, mechanical constraints, and many other considerations
Addressing these new challenges calls for adaptations in your design flow and signoff/analysis flow.
Design Flow for 3D-ICs
If your design team is like most, there could be digital engineers and analog/mixed-signal engineers responsible for 3D-IC design. Cadence’s digital design and signoff flow is part of our comprehensive infrastructure for 3D-IC design.
Cadence provides a single source of IP, implementation, test, analysis, and verification products that address the challenges of 3D-IC design for digital SoCs, analog/mixed-signal designs, and entire systems. Many of these tools are integrated and feature a common UI to help enhance your design productivity.
To efficiently plan and assess connectivity and route feasibility in your 3D-IC design, look to Cadence OrbitIO™ Interconnect Designer. You’ll be able to quickly evaluate the connectivity between the die and package in the context of your full system. You’ll also be equipped to make or refine decisions and, right away, visualize the impact on adjacent fabrics within this single tool. This capability will help you cut down on iterations between silicon and package design teams.
When you’re ready to test, look to our Genus™ Synthesis Solution and Modus™ Test products for logic die design for test (DFT). Using these tools, you can perform a DFT insertion to test the die-to-die interconnect, including silicon interposers.
For logic die implementation, look to our Innovus™ Implementation System and our Physical Verification System. With unique capabilities in place and route, optimization, and clocking, the Innovus Implementation System delivers production-proven power, performance, and area (PPA) advantages as well as faster turnaround times. An Innovus plug-in provides functions for 3D-IC designs, including creation of TSVs and micro-bumps. Physical Verification System (PVS) can perform design rule checking (DRC) as well as layout vs. schematic (LVS) that runs multiple die verification concurrently.
If your design also contains analog components, you can use this same flow. Integrated into this flow, our Virtuoso® custom design platform can support custom 3D-IC realization, from TSV feed-through implementation on the memory die to the mapping of memory die bumps to the logic die.
Cadence’s OpenAccess database provides a natively unified database for inter-operation between the Innovus and Virtuoso platforms. For example, in a typical interposer design that contains many bus signals that require not only minimal delay but also delay matching, using the slack-driven routing technology in the Innovus Implementation System as well as Virtuoso Space-Based Router may yield better implementation results.
Cadence SiP Layout can also help with silicon interposer design. It can even display both silicon layers and package layers in a single design window for easier viewing and editing, providing a great platform for packaging engineers to do multi-die integration.
Signoff and Analysis Flow for 3D-ICs
In the analysis and signoff phase, you’ll need to validate your design, ensuring that the inter-die in your 3D implementation is correct. You can use our Physical Verification System to perform a cross die check. You’ll also need to evaluate electrical performance. On the digital side, we offer an array of tools for extraction and timing and power signoff:
- Quantus™ QRC Extraction Solution provides parasitic extraction and analysis for TSVs, micro-bumps, and other characteristics associated with 3D technologies
- Tempus™ Timing Signoff Solution provides silicon-accurate timing signoff and signal integrity analysis across multiple dies
- Voltus™ IC Power Integrity Solution provides not only a single full-chip, but also the entire multi-die, 3D-IC system in a package
Cadence offers a unique capability for thermal management of 3D-IC designs. Our Voltus IC Power Integrity Solution generates a power map that is then fed into Cadence Sigrity™ PowerDC technology, the thermal analyzer that takes power consumption data and determines the temperature distribution for each die. This data then goes back to the Voltus solution for temperature-dependent IR-drop analysis. If you need to run thermal analysis through many iterations, the Voltus solution provides a GUI that allows you to invoke the thermal engine within the solution to get the temperature results automatically displayed at the die level.
For More Information
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